Dual 12-Bit, High Bandwidth, Multiplying DAC with 4-Quadrant Resistors and Parallel Interface Data Sheet AD5405 FEATURES GENERAL DESCRIPTION 1 10 MHz multiplying bandwidth The AD5405 is a CMOS, 12-bit, dual-channel, current output On-chip 4-quadrant resistors allow flexible output ranges digital-to-analog converter (DAC). This device operates from a INL of 1 LSB 2.5 V to 5.5 V power supply, making it suited to battery-powered 40-lead LFCSP package and other applications. 2.5 V to 5.5 V supply operation Because of manufacturing with a CMOS submicron process, the 10 V reference input device offers excellent 4-quadrant multiplication characteristics, 21.3 MSPS update rate with large signal multiplying bandwidths of up to 10 MHz. Extended temperature range: 40C to +125C The applied external reference input voltage (V ) determines REF 4-quadrant multiplication the full-scale output current. An integrated feedback resistor (R ) FB Power-on reset provides temperature tracking and full-scale voltage output when 0.5 A typical current consumption combined with an external I to V precision amplifier. This device Guaranteed monotonic also contains the 4-quadrant resistors necessary for bipolar Readback function operation and other configuration modes. APPLICATIONS This DAC uses data readback, allowing the user to read the Portable battery-powered applications contents of the DAC register via the DB pins. On power-up, the Waveform generators internal register and latches fill with 0s, and the DAC outputs Analog processing are at zero scale. Instrumentation applications The AD5405 has a 6 mm 6 mm, 40-lead LFCSP package. Programmable amplifiers and attenuators Digitally controlled calibration 1 U.S. Patent Number 5,689,257. Programmable filters and oscillators Composite video Ultrasound Gain, offset, and voltage trimming FUNCTIONAL BLOCK DIAGRAM V A R3A R2 3A R2A REF R1A R3 R2 2R 2R R1 RFB AD5405 2R 2R V R A DD FB DATA DB0 I 1A OUT INPUTS INPUT 12-BIT LATCH BUFFER R-2R DAC A DB11 I 2A OUT DAC A/B CONTROL CS LOGIC R/W I 1B OUT 12-BIT LATCH R-2R DAC B I 2B OUT LDAC R B FB GND POWER-ON R1 RFB RESET 2R 2R R3 R2 CLR 2R 2R R3B R2 3B R2B V B R1B REF Figure 1. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20042018 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. 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Technical Support www.analog.com 04463-001AD5405 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Circuit Operation ....................................................................... 14 Applications ....................................................................................... 1 Single-Supply Applications ....................................................... 15 General Description ......................................................................... 1 Adding Gain ................................................................................ 15 Functional Block Diagram .............................................................. 1 Divider or Programmable Gain Element ................................ 16 Revision History ............................................................................... 2 Reference Selection .................................................................... 16 Specifications ..................................................................................... 3 Amplifier Selection .................................................................... 16 Timing Characteristics ................................................................ 5 Parallel Interface ......................................................................... 18 Absolute Maximum Ratings ............................................................ 6 Microprocessor Interfacing ....................................................... 18 ESD Caution .................................................................................. 6 PCB Layout and Power Supply Decoupling ........................... 19 Pin Configuration and Function Descriptions ............................. 7 Overview of the AD5424 to AD5547 Devices ............................ 22 Typical Performance Characteristics ............................................. 8 Outline Dimensions ....................................................................... 23 Terminology .................................................................................... 13 Ordering Guide .......................................................................... 23 General Description ....................................................................... 14 DAC Section ................................................................................ 14 REVISION HISTORY 7/2018Rev. C to Rev. D 7/2005Rev. 0 to Rev. A Changes to Pin 2 and Pin 3, Mnemonic Column, Table 4 .......... 7 Changed Pin DAC A/B to DAC /B ............................... Universal A Changes to Features List ................................................................... 1 1/2016Rev. B to Rev. C Changes to Specifications ................................................................. 3 Deleted Positive Output Voltage Section and Figure 35............ 15 Changes to Timing Characteristics ................................................. 5 Changes to Adding Gain Section ................................................. 15 Change to Absolute Maximum Ratings ......................................... 6 Changes to ADSP-21xx Processors to AD5405 Interface Section Change to Figure 7 and Figure 8 ..................................................... 8 Title, ADSP-BF504 to ADSP-BF592 Device Family to AD5405 Change to Figure 12 .......................................................................... 9 Interface Section Title, and Figure 39 Caption ........................... 19 Change to Figure 26 Through Figure 28 ..................................... 11 Deleted Evaluation Board for the DACs Section and Power Changes to General Description Section .................................... 14 Supplies for the Evaluation Board Section .................................. 19 Change to Figure 31 ....................................................................... 14 Changes to Table 10 ........................................................................ 22 Changes to Table 5 Through Table 10 ......................................... 14 Updated Outline Dimensions ....................................................... 23 Changes to Figure 34 and Figure 35 ............................................ 15 Changes to Ordering Guide .......................................................... 23 Changes to Figure 36 and Figure 37 ............................................ 16 Changes to Microprocessor Interfacing Section ........................ 18 12/2009Rev. A to Rev. B Added Figure 38 Through Figure 40 ........................................... 18 Changes to Figure 1 .......................................................................... 1 Change to Power Supplies for the Evaluation Board Section ... 19 Changes to Table 2 and Figure 2 ..................................................... 5 Updated Outline Dimensions ....................................................... 23 Changes to Table 4 and Figure 4 ..................................................... 7 Changes to Ordering Guide .......................................................... 23 Updated Outline Dimensions ....................................................... 23 Changes to Ordering Guide .......................................................... 23 7/2004Revision 0: Initial Version Rev. D Page 2 of 24