Dual 8-/10-/12-Bit, High Bandwidth, Multiplying DACs with Serial Interface Data Sheet AD5429/AD5439/AD5449 FEATURES GENERAL DESCRIPTION 1 10 MHz multiplying bandwidth The AD5429/AD5439/AD5449 are CMOS, 8-, 10-, and 12-bit, INL of 0.25 LSB at 8 bits dual-channel, current output digital-to-analog converters (DAC), 16-lead TSSOP package respectively. These devices operate from a 2.5 V to 5.5 V power 2.5 V to 5.5 V supply operation supply, making them suited to battery-powered and other 10 V reference input applications. 50 MHz serial interface As a result of being manufactured on a CMOS submicron process, 2.47 MSPS update rate these parts offer excellent 4-quadrant multiplication character- Extended temperature range: 40C to +125C 4-quadrant multiplication istics, with large signal multiplying bandwidths of 10 MHz. Power-on reset The applied external reference input voltage (V ) determines REF 0.5 A typical current consumption the full-scale output current. An integrated feedback resistor Guaranteed monotonic (RFB) provides temperature tracking and full-scale voltage Daisy-chain mode output when combined with an external current-to-voltage Readback function precision amplifier. APPLICATIONS These DACs use a double-buffered, 3-wire serial interface that Portable battery-powered applications is compatible with SPI, QSPI, MICROWIRE, and most DSP Waveform generators interface standards. In addition, a serial data out (SDO) pin allows Analog processing daisy-chaining when multiple packages are used. Data readback Instrumentation applications allows the user to read the contents of the DAC register via the Programmable amplifiers and attenuators SDO pin. On power-up, the internal shift register and latches Digitally controlled calibration are filled with 0s, and the DAC outputs are at zero scale. Programmable filters and oscillators Composite video The AD5429/AD5439/AD5449 DACs are available in 16-lead Ultrasound TSSOP packages. The EV-AD5415/49SDZ evaluation board is Gain, offset, and voltage trimming available for evaluating DAC performance. For more information, see the UG-297 evaluation board user guide. FUNCTIONAL BLOCK DIAGRAM V A REF RFB AD5429/AD5439/AD5449 R V DD R A FB SYNC I 1A OUT SHIFT INPUT DAC 8-/10-/12-BIT SCLK REGISTER REGISTER REGISTER R-2R DAC A I 2A OUT SDIN SDO LDAC CLR I 1B OUT INPUT DAC 8-/10-/12-BIT POWER-ON REGISTER REGISTER R-2R DAC B RESET I 2B OUT R B FB RFB R LDAC V B REF Figure 1. 1 U.S. Patent Number 5,689,257. Rev. F Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20042016 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 04464-001AD5429/AD5439/AD5449 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Digital-to-Analog Converter .................................................... 15 Applications ....................................................................................... 1 Circuit Operation ....................................................................... 15 General Description ......................................................................... 1 Single-Supply Applications ....................................................... 17 Functional Block Diagram .............................................................. 1 Adding Gain ................................................................................ 18 Revision History ............................................................................... 2 Divider or Programmable Gain Element ................................ 18 Specif icat ions ..................................................................................... 3 Reference Selection .................................................................... 19 Timing Characteristics ................................................................ 5 Amplifier Selection .................................................................... 19 Timing Diagrams .......................................................................... 5 Serial Interface ............................................................................ 20 Absolute Maximum Ratings ............................................................ 7 Microprocessor Interfacing ....................................................... 22 ESD Caution .................................................................................. 7 PCB Layout and Power Supply Decoupling ........................... 24 Pin Configuration and Function Descriptions ............................. 8 Overview of Multiplying DAC Devices ....................................... 25 Typical Performance Characteristics ............................................. 9 Outline Dimensions ....................................................................... 26 Terminology .................................................................................... 14 Ordering Guide .......................................................................... 26 Theory of Operation ...................................................................... 15 REVISION HISTORY 7/05Rev. 0 to Rev. A 1/16Rev. E to Rev. F Changes to Features List ................................................................... 1 Changed AD54xx to AD5429/AD5439/AD5449 ........... Throughout Changes to Specifications ................................................................. 3 Changed ADSP-21xx to ADSP-2191M and Family ........ Throughout Changes to Timing Characteristics ................................................. 5 Changed ADSP-2101/ADSP-2103/ADSP-2191 to Changes to Absolute Maximum Ratings Section .......................... 7 ADSP-2191M ................................................................. Throughout Changes to General Description Section .................................... 15 Changed ADSP-BF5xx to ADSP-BF534 ........................... Throughout Changes to Table 5 .......................................................................... 15 Deleted Positive Output Voltage Section and Figure 41 Changes to Table 6 .......................................................................... 16 Renumbered Sequentially .............................................................. 17 Changes to Single-Supply Applications Section ......................... 17 Changes to Adding Gain Section ................................................. 18 Changes to Divider or Programmable Gain Element Section .... 18 Changed Overview of AD54xx Devices Section to Overview Changes to Table 7 Through Table 10 ......................................... 20 of Multiplying DAC Devices Section ........................................... 26 Added ADSP-BF5xx-to-AD5429/AD5439/AD5449 Interface S ection .............................................................................................. 23 5/13Rev. D to Rev. E Change to PCB Layout and Power Supply Decoupling Section ..... 25 Changes to General Description .................................................... 1 Changes to Power Supplies for the Evaluation Board Section .... 25 Changes to Ordering Guide .......................................................... 26 Changes to Table 13 ....................................................................... 29 Updated Outline Dimensions ....................................................... 30 6/11Rev. C to Rev. D Changes to Ordering Guide .......................................................... 30 Changes to General Description .................................................... 1 Deleted Evaluation Board for the DAC Section ......................... 24 7/04Revision 0: Initial Version Changes to Ordering Guide .......................................................... 30 4/10Rev. B to Rev. C Added to Figure 4 ............................................................................. 6 3/08Rev. A to Rev. B Added t and t Parameters to Table 2 ......................................... 5 13 14 Changes to Figure 2 .......................................................................... 5 Changes to Figure 3 .......................................................................... 6 Changes to Figure 38 ...................................................................... 16 Changes to Ordering Guide .......................................................... 30 Rev. F Page 2 of 28