Dual 8-/10-/12-Bit, High Bandwidth, Multiplying DACs with Parallel Interface Data Sheet AD5428/AD5440/AD5447 FEATURES GENERAL DESCRIPTION 1 10 MHz multiplying bandwidth The AD5428/AD5440/AD5447 are CMOS, 8-, 10-, and 12-bit, INL of 0.25 LSB at 8 bits dual-channel, current output digital-to-analog converters (DACs), 20-lead and 24-lead TSSOP packages respectively. These devices operate from a 2.5 V to 5.5 V power 2.5 V to 5.5 V supply operation supply, making them suited to battery-powered and other 10 V reference input applications. 21.3 MSPS update rate As a result of being manufactured on a CMOS submicron process, Extended temperature range: 40C to +125C they offer excellent 4-quadrant multiplication characteristics, 4-quadrant multiplication with large signal multiplying bandwidths of up to 10 MHz. Power-on reset The DACs use data readback, allowing the user to read the 0.5 A typical current consumption contents of the DAC register via the DB pins. On power-up, the Guaranteed monotonic internal register and latches are filled with 0s, and the DAC Readback function outputs are at zero scale. AD7528 upgrade (AD5428) AD7547 upgrade (AD5447) he applied external reference input voltage (V ) determines REF the full-scale output current. An integrated feedback resistor (R ) APPLICATIONS FB provides temperature tracking and full-scale voltage output when Portable battery-powered applications combined with an external I-to-V precision amplifier. Waveform generators The AD5428 is available in a small 20-lead TSSOP package, and Analog processing Instrumentation applications the AD5440/AD5447 DACs are available in small 24-lead TSSOP Programmable amplifiers and attenuators packages. Digitally controlled calibration Programmable filters and oscillators Composite video Ultrasound Gain, offset, and voltage trimming FUNCTIONAL BLOCK DIAGRAM V A REF AD5428/AD5440/AD5447 R V R A DD FB DB0 DATA I A OUT INPUT INPUTS 8-/10-/12-BIT LATCH BUFFER R-2R DAC A DB7 DB9 DB11 AGND DAC A/B R R B CONTROL FB CS LOGIC I B R/W OUT 8-/10-/12-BIT LATCH R-2R DAC B DGND POWER-ON RESET V B REF Figure 1. 1 U.S. Patent Number 5,689,257. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20042016 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 04462-001AD5428/AD5440/AD5447 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Single-Supply Applications ....................................................... 19 Applications ....................................................................................... 1 Adding Gain ................................................................................ 19 General Description ......................................................................... 1 Divider or Programmable Gain Element ................................ 20 Functional Block Diagram .............................................................. 1 Reference Selection .................................................................... 20 Revision History ............................................................................... 2 Amplifier Selection .................................................................... 20 Specif icat ions ..................................................................................... 3 Parallel Interface ......................................................................... 22 Timing Characteristics ................................................................ 5 Microprocessor Interfacing ....................................................... 22 Absolute Maximum Ratings ............................................................ 6 PCB Layout and Power Supply Decoupling ........................... 23 ESD Caution .................................................................................. 6 Evaluation Board for the AD5447 ............................................ 23 Pin Configurations and Function Descriptions ........................... 7 Power Supplies for the Evaluation Board ................................ 23 Typical Performance Characteristics ........................................... 10 Bill of Materials ............................................................................... 27 Terminology .................................................................................... 15 Overview of Multiplying DAC Devices ....................................... 28 General Description ....................................................................... 16 Outline Dimensions ....................................................................... 29 DAC Section ................................................................................ 16 Ordering Guide .......................................................................... 30 Circuit Operation ....................................................................... 16 REVISION HISTORY 1/16Rev. C. to Rev. D Change to Absolute Maximum Ratings Section ........................... 6 Changed ADSP-21xx to ADSP-2191M ......................... Throughout Change to Figure 13, Figure 14, and Figure 18 ........................... 11 Change to Figure 32 Through Figure 34 ..................................... 14 Changed ADSP-BF5xx to ADSP-BF534 ..................... Throughout Deleted Positive Output Voltage Section and Figure 41 ............ 19 Changes to General Description Section .................................... 16 Changes to Adding Gain Section ................................................. 19 Changes to Figure 37 ...................................................................... 16 Changes to Ordering Guide .......................................................... 30 Changes to Single-Supply Applications Section ......................... 19 Changes to Figure 40 Through Figure 42.................................... 19 8/11Rev. B to Rev. C Changes to Divider or Programmable Gain Element Section .... 20 CS Changes to Figure 43 ...................................................................... 20 Changes to Pin Description, Table 6 ........................................ 9 Changes to Table 9 Through Table 11 ......................................... 21 Changes to Microprocessor Interfacing Section ........................ 22 3/11Rev. A to Rev. B Added Figure 44 Through Figure 46 ........................................... 22 Changes to Evaluation Board For the AD5447 Section ............ 23 Added 8xC51-to-AD5428/AD5440/AD5447 Changes to Figure 47 Caption ....................................................... 24 Interface Section ........................................................................ 22 Changes to Figure 49 ...................................................................... 25 Added ADSP-BF5xx-to-AD5428/AD5440/AD5447 Change to U1 Description in Table 12......................................... 27 Interface Section ........................................................................ 22 Change to Ordering Guide ............................................................ 29 Changes to Power Supplies for the Evaluation Board Section .... 23 Changes to Table 13 ....................................................................... 28 7/05Rev. 0 to Rev. A Updated Outline Dimensions ....................................................... 29 Changed Pin DAC A/B to DAC A/B ................................ Univers a l Changes to Ordering Guide .......................................................... 29 Changes to Features List .................................................................. 1 Changes to Specifications ................................................................ 3 7/04Revision 0: Initial Version Changes to Timing Characteristics ................................................ 5 Change to Figure 2 ........................................................................... 5 Rev. D Page 2 of 32