32-Channel, 14-Bit Voltage-Output DAC AD5532 FEATURES GENERAL DESCRIPTION High integration: 1 The AD5532 is a 32-channel, 14-bit voltage-output DAC with 32-channel DAC in 12 mm 12 mm CSPBGA an additional infinite sample-and-hold mode. The selected Adjustable voltage output range DAC register is written to via the 3-wire serial interface VOUT Guaranteed monotonic for this DAC is then updated to reflect the new contents of the Readback capability DAC register. DAC selection is accomplished via Address Bits DSP/microcontroller compatible serial interface A0A4. The output voltage range is determined by the offset Output impedance: voltage at the OFFS IN pin and the gain of the output amplifier. 0.5 (AD5532-1, AD5532-2) It is restricted to a range from V + 2 V to V 2 V because of SS DD 500 (AD5532-3) the headroom of the output amplifier. 1 k (AD5532-5) = 5 V 5% DV = 2.7 V to Output voltage span: The device is operated with AVCC CC 10 V (AD5532-1, AD5532-3, AD5532-5) 5.25 V VSS = 4.75 V to 16.5 V and VDD = 8 V to 16.5 V. The AD5532 requires a stable 3 V reference on REF IN as well as an 20 V (AD5532-2) offset voltage on OFFS IN. Infinite sample-and-hold capability to 0.018% accuracy Temperature range 40C to +85C PRODUCT HIGHLIGHTS APPLICATIONS 1. 32-channel, 14-bit DAC in one package, guaranteed Automatic test equipment monotonic. Optical networks 2. Available in a 74-lead CSPBGA package with a body size of Level setting 12 mm 12 mm. Instrumentation 3. Droopless/infinite sample-and-hold mode. Industrial control systems Data acquisition Low cost I/O DV REF IN REF OUT OFFS IN V V AV CC CC DD SS AD5532 V 0 OUT V IN ADC DAC TRACK/RESET BUSY V 31 OUT MUX DAC DAC GND AGND OFFS OUT DAC DGND INTERFACE CONTROL SER/PAR ADDRESS INPUT REGISTER WR LOGIC SCLK D D SYNC/CS A4A0 CAL OFFSET SEL IN OUT Figure 1. Functional Block Diagram Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 www.analog.com or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.326.8703 2010 Analog Devices, Inc. All rights reserved. MODE 14-BIT BUS 00939-C-001AD5532 TABLE OF CONTENTS Specif icat ions ..................................................................................... 3 Output Buffer StageGain and Offset.................................... 14 ISHA Mode .................................................................................... 5 Offset Voltage Channel .............................................................. 14 Timing Characteristics ..................................................................... 6 Reset Function ............................................................................ 14 Parallel Interface ........................................................................... 6 ISHA Mode ................................................................................. 14 Parallel Interface Timing Diagrams ........................................... 6 Analog Input (ISHA Mode) ...................................................... 14 Serial Interface .............................................................................. 7 Function (ISHA Mode) .............................................. 15 TRACK Absolute Maximum Ratings ............................................................ 8 Modes of Operation ................................................................... 15 ESD Caution .................................................................................. 8 Serial Interface ............................................................................ 16 Pin Configuration and Function Descriptions ............................. 9 Parallel Interface (ISHA Mode Only) ...................................... 17 Terminology .................................................................................... 11 Microprocessor Interfacing ....................................................... 17 Dac Mode .................................................................................... 11 Application Circuits ................................................................... 18 ISHA Mode .................................................................................. 11 Power Supply Decoupling ......................................................... 19 Typical Performance Characteristics ........................................... 12 Outline Dimensions ....................................................................... 20 Functional Description .................................................................. 14 Ordering Guide .......................................................................... 20 REVISION HISTORY 6/10Data Sheet Changed from Rev. C to Rev. D Changes to Table 5 ...................................................................... 8 Changes to Ordering Guide .................................................... 20 6/04Data Sheet Changed from Rev. B to Rev. C Updated Format ........................................................... Universal Changed LFBGA to CSPBGA .................................... Universal Changes to Outline Dimensions ............................................. 24 Changes to Ordering Guide .................................................... 24 6/02Data Sheet Changed from Rev. A to Rev. B Term SHA changed to ISHA ........................................... Global Changes to Absolute Maximum Ratings ................................. 6 Changes to Ordering Guide ...................................................... 6 Changes to Functional Description ....................................... 11 Changes to Table 8 .................................................................... 11 Changes to ISHA Mode ........................................................... 11 Added Figure 27 and accompanying text .............................. 15 Changes to Power Supply Decoupling Section ..................... 15 Rev. D Page 2 of 20