2.7 V to 5.5 V, <100 A, 14-Bit nanoDAC,
SPI Interface in LFCSP and SC70
Data Sheet
AD5641
FEATURES FUNCTIONAL BLOCK DIAGRAM
V
DD GND
6-lead LFCSP and SC70 packages
Micropower operation: 100 A maximum at 5 V
POWER-ON
AD5641
Power-down to typically 0.2 A at 3 V
RESET
Single 14-bit DAC
B version: 4 LSB INL
REF(+)
DAC
OUTPUT
14-BIT V
OUT
A version: 16 LSB INL
REGISTER
BUFFER
DAC
2.7 V to 5.5 V power supply
Guaranteed monotonic by design
Power-on reset to 0 V with brownout detection
INPUT
POWER-DOWN
CONTROL
RESISTOR
3 power-down functions CONTROL LOGIC
LOGIC
NETWORK
Low power serial interface with Schmitt-triggered inputs
On-chip output buffer amplifier, rail-to-rail operation
SYNC interrupt facility
SYNC SCLK SDIN
APPLICATIONS
Figure 1.
Voltage level setting
Portable battery-powered instruments
Digital gain and offset adjustment
Table 1. Related Devices
Programmable voltage and current sources
Part Number Description
Programmable attenuators
AD5601 2.7 V to 5.5 V, <100 A, 8-bit nanoDAC,
SPI interface in LFCSP and SC70 packages
GENERAL DESCRIPTION
AD5611 2.7 V to 5.5 V, <100 A, 10-bit nanoDAC,
The AD5641, a member of the nanoDAC family, is a single,
SPI interface in LFCSP and SC70 packages
14-bit, buffered, voltage-out DAC that operates from a single
AD5621 2.7 V to 5.5 V, <100 A, 12-bit nanoDAC,
2.7 V to 5.5 V supply, typically consuming 75 A at 5 V. The
SPI interface in LFCSP and SC70 packages
part comes in tiny LFCSP and SC70 packages. Its on-chip
precision output amplifier allows rail-to-rail output swing to be
achieved. The AD5641 uses a versatile 3-wire serial interface PRODUCT HIGHLIGHTS
that operates at clock rates up to 30 MHz and is compatible with
1. Available in space-saving 6-lead LFCSP and SC70
SPI, QSPI, MICROWIRE, and DSP interface standards. The
packages.
reference for AD5641 is derived from the power supply inputs
2. Low power, single-supply operation. The AD5641 operates
and, therefore, gives the widest dynamic output range. The part
from a single 2.7 V to 5.5 V supply and with a maximum
incorporates a power-on reset circuit, which ensures that the
current consumption of 100 A, making it ideal for
DAC output powers up to 0 V and remains there until a valid
battery-powered applications.
write to the device takes place.
3. The on-chip output buffer amplifier allows the output of
The AD5641 contains a power-down feature that reduces the DAC to swing rail-to-rail with a typical slew rate of
current consumption typically to 0.2 A at 3 V, and provides 0.5 V/s.
4. Reference derived from the power supply.
software-selectable output loads while in power-down mode.
5. High speed serial interface with clock speeds up to
The part is put into power-down mode over the serial interface.
30 MHz. Designed for very low power consumption. The
The low power consumption of the part in normal operation
makes it ideally suited to portable battery-operated equipment. interface powers up only during a write cycle.
The combination of small package and low power makes this 6. Power-down capability. When powered down, the DAC
nanoDAC device ideal for level-setting requirements such as typically consumes 0.2 A at 3 V.
generating bias or control voltages in space-constrained and 7. Power-on reset with brownout detection.
power-sensitive applications.
Rev. D
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Last Content Update: 02/23/2017
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AD5641: 2.7 V to 5.5 V, <100 A, 14-Bit nanoDAC, SPI
Interface in LFCSP and SC70 Data Sheet
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