Quad, 16-Bit DAC with 5 ppm/C On-Chip Reference in 14-Lead TSSOP AD5666 FEATURES FUNCTIONAL BLOCK DIAGRAM V /V V REFIN REFOUT DD Low power quad 16-bit DAC AD5666 1.25V/2.5V 14-lead TSSOP REF LDAC BUFFER On-chip 1.25 V/2.5 V, 5 ppm/C reference INPUT DAC STRING V A OUT REGISTER REGISTER DAC A SCLK Power down to 400 nA 5 V, 200 nA 3 V BUFFER INPUT DAC STRING V B OUT REGISTER REGISTER DAC B INTERFACE 2.7 V to 5.5 V power supply SYNC LOGIC BUFFER INPUT DAC STRING V C OUT Guaranteed monotonic by design REGISTER REGISTER DAC C DIN BUFFER DAC STRING Power-on reset to zero scale or midscale INPUT V D OUT REGISTER REGISTER DAC D SDO 3 power-down functions POWER-ON POWER-DOWN LOGIC RESET Hardware LDAC with LDAC override function POR GND LDAC CLR CLR function to programmable code Figure 1. SDO daisy-chaining option Rail-to-rail operation APPLICATIONS Process control Data acquisition systems Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources Programmable attenuators GENERAL DESCRIPTION The AD5666 is a low power, quad, 16-bit, buffered voltage- The outputs of all DACs can be updated simultaneously using output DAC. The part operates from a single 2.7 V to 5.5 V the LDAC function, with the added functionality of user-select- supply and is guaranteed monotonic by design. able DAC channels to simultaneously update. There is also an asynchronous that clears all DACs to a software-selectable CLR The AD5666 has an on-chip reference with an internal gain of 2. code0 V, midscale, or full scale. The AD5666-1 has a 1.25 V 5 ppm/C reference, giving a full-scale output of 2.5 V the AD5666-2 has a 2.5 V 5 ppm/C reference, The AD5666 utilizes a versatile 3-wire serial interface that operates giving a full-scale output of 5 V. The on-board reference is off at at clock rates of up to 50 MHz and is compatible with standard power-up, allowing the use of an external reference. The internal SPI, QSPI, MICROWIRE, and DSP interface standards. The reference is turned on by writing to the DAC. on-chip precision output amplifier enables rail-to-rail output swing. The part incorporates a power-on reset circuit that ensures that the DAC output powers up to 0 V (POR pin low) or to midscale PRODUCT HIGHLIGHTS (POR pin high) and remains powered up at this level until a valid 1. Quad, 16-bit DAC. write takes place. The part contains a power-down feature that 2. On-chip 1.25 V/2.5 V, 5 ppm/C reference. reduces the current consumption of the device to 400 nA at 5 V 3. Available in 14-lead TSSOP. and provides software-selectable output loads while in power-down 4. Selectable power-on reset to 0 V or midscale. mode for any or all DAC channels. 5. Power-down capability. When powered down, the DAC typically consumes 200 nA at 3 V and 400 nA at 5 V. Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 20052010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 05298-001AD5666 TABLE OF CONTENTS Features .............................................................................................. 1 Resistor String ............................................................................. 20 Applications ....................................................................................... 1 Internal Reference ...................................................................... 20 Functional Block Diagram .............................................................. 1 Output Amplifier ........................................................................ 21 General Description ......................................................................... 1 Serial Interface ............................................................................ 21 Product Highlights ........................................................................... 1 Input Shift Register .................................................................... 22 Revision History ............................................................................... 2 Interrupt .......................................................................... 22 SYNC Specif icat ions ..................................................................................... 3 Daisy-Chaining ........................................................................... 23 AC Characteristics ........................................................................ 7 Internal Reference Register ....................................................... 23 Timing Characteristics ................................................................ 8 Power-On Reset .......................................................................... 23 Absolute Maximum Ratings .......................................................... 10 Power-Down Modes .................................................................. 23 ESD Caution ................................................................................ 10 Clear Code Register ................................................................... 25 Pin Configuration and Function Descriptions ........................... 11 Function .......................................................................... 25 LDAC Typical Performance Characteristics ........................................... 12 Power Supply Bypassing and Grounding ................................ 25 Terminology .................................................................................... 18 Outline Dimensions ....................................................................... 27 Theory of Operation ...................................................................... 20 Ordering Guide .......................................................................... 27 D/A Section ................................................................................. 20 REVISION HISTORY 6/10Rev. C to Rev. D Changes to Figure 19 and Figure 20 Captions ............................ 14 10/09Rev. B to Rev. C Changes to Table 7 .......................................................................... 21 2/09Rev. A to Rev. B Changes to Reference Current Parameter, Table 1 ....................... 3 Changes to Reference Current Parameter, Table 2 ....................... 5 Updated Outline Dimensions ....................................................... 27 11/05Rev. 0 to Rev. A Change to General Description ...................................................... 1 Change to Specifications .................................................................. 3 10/05Revision 0: Initial Version Rev. D Page 2 of 28