16-Channel, 12-/16-Bit nanoDAC+ with 2 ppm/C Voltage Reference Temperature Coefficient, SPI Interface Data Sheet AD5674/AD5674R/AD5679/AD5679R FEATURES FUNCTIONAL BLOCK DIAGRAM VLOGIC VDD VREF High performance AD5679R/AD5679/AD5674R/AD5674 High relative accuracy (INL): 4 LSB maximum at 16 bits 1 2.5V REF BUFFER (AD5679/AD5679R) INPUT DAC STRING VOUT0 REGISTER REGISTER DAC 0 TUE: 0.14% of FSR maximum BUFFER Offset error: 1.5 mV maximum INPUT DAC STRING VOUT1 REGISTER REGISTER DAC 1 SCLK Gain error: 0.06% of FSR maximum BUFFER INPUT DAC STRING VOUT2 Low drift, 2.5 V voltage reference temperature coefficient: REGISTER REGISTER DAC 2 SYNC 2 ppm/C typical BUFFER INPUT DAC STRING VOUT3 REGISTER REGISTER DAC 3 40 mA short-circuit current SDI Wide operating ranges 40C to +125C temperature range BUFFER SDO INPUT DAC STRING VOUT14 REGISTER REGISTER DAC 14 2.7 V to 5.5 V power supply range BUFFER Simplified implementation INPUT DAC STRING LDAC VOUT15 REGISTER REGISTER DAC 15 User selectable gain of 1 or 2 (GAIN pin) RESET POWER-ON GAIN POWER-DOWN 1.8 V logic compatibility RESET 1/2 LOGIC 50 MHz serial peripheral interface (SPI) with readback or 1 GAIN GND ONLY APPLICABLE TO AD5679R/AD5674R. daisy chain Figure 1. 28-lead, 4 mm 4 mm, RoHS compliant LFCSP APPLICATIONS Optical transceivers Base station power amplifiers Process control (programmable logic controller (PLC) input/output cards) Industrial automation Data acquisition systems GENERAL DESCRIPTION The AD5674/AD5674R/AD5679/AD5679R are low power, Table 1. Octal and 16-Channel nanoDAC+ Devices 16-channel, 12-/16-bit, buffered voltage output, digital-to- No. of analog converters (DACs) that include a 2.5 V, 2 ppm/C internal Channels Interface Reference 16-Bit 12-Bit 1 reference (enabled by default), and a gain select pin, resulting 8 SPI Internal AD5676R AD5672R in a full-scale output of 2.5 V (gain = 1) or 5 V (gain = 2). The External AD5676 Not devices operate from a single, 2.7 V to 5.5 V supply range and applicable 2 are guaranteed monotonic by design. The AD5674/AD5674R/ IC Internal AD5675R AD5671R AD5679/AD5679R are available in a 28-lead lead frame chip scale 16 SPI Internal AD5679R AD5674R package (LFCSP) and incorporate a power-on reset (POR) circuit External AD5679 AD5674 that ensures that the DAC outputs power up to and remains at PRODUCT HIGHLIGHTS zero-scale or midscale until a valid write. The AD5674/AD5674R/ 1. High channel density: 16 channels in 4 mm 4 mm AD5679/AD5679R contain a power-down mode that reduces LFCSP. the current consumption to 2 A typical. 2. High relative accuracy (integral nonlinearity (INL)) 4 LSB maximum. 3. Low drift, 2.5 V, on-chip reference. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. Tel: 781.329.4700 2019 Analog Devices, Inc. All rights reserved. No license is granted by implication or otherwise under any patent or patent rights of Analog Technical Support www.analog.com Devices. Trademarks and registered trademarks are the property of their respective owners. INTERFACE LOGIC 17326-001AD5674/AD5674R/AD5679/AD5679R Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Write and Update Commands .................................................. 25 Applications ....................................................................................... 1 Daisy-Chain Operation ............................................................. 25 Functional Block Diagram .............................................................. 1 Readback Operation .................................................................. 25 General Description ......................................................................... 1 Power-Down Operation ............................................................ 26 Product Highlights ........................................................................... 1 LDAC Load DAC (Hardware Pin) ........................................... 27 Revision History ............................................................................... 2 LDAC Mask Register ................................................................. 27 Specifications ..................................................................................... 3 Hardware Reset (RESET) .......................................................... 28 AD5674/AD5674R Specifications .............................................. 3 Power-On Reset Internal Circuit.............................................. 28 AD5679/AD5679R Specifications .............................................. 5 Software Reset ............................................................................. 28 AC Characteristics ........................................................................ 7 Internal Reference Setup ........................................................... 28 Timing Characteristics ................................................................ 7 Solder Heat Reflow ..................................................................... 28 Daisy-Chain and Readback Timing Characteristics................ 8 Long-Term Temperature Drift ................................................. 29 Absolute Maximum Ratings .......................................................... 10 Thermal Hysteresis .................................................................... 29 Thermal Resistance .................................................................... 10 Applications Information .............................................................. 30 ESD Caution ................................................................................ 10 Power Supply Recommendations ............................................. 30 Pin Configuration and Function Descriptions ........................... 11 Microprocessor Interfacing ....................................................... 30 Typical Performance Characteristics ........................................... 12 AD5674/AD5674R/AD5679/AD5679R to ADSP-BF531 Interface ....................................................................................... 30 Terminology .................................................................................... 21 AD5674/AD5674R/AD5679/AD5679R to SPORT Interface 30 Theory of Operation ...................................................................... 23 Layout Guidelines....................................................................... 30 DAC .............................................................................................. 23 Galvanically Isolated Interface ................................................. 31 Transfer Function ....................................................................... 23 Outline Dimensions ....................................................................... 32 DAC Architecture ....................................................................... 23 Ordering Guide .......................................................................... 32 Serial Interface ............................................................................ 23 Standalone Operation ................................................................ 25 REVISION HISTORY 12/2019Rev. A to Rev. B Changes to General Description .................................................... 1 Changes to Functional Block Diagram, Table 1, General Table 2 and Endnote 1 ...................................................................... 4 Description Section, and Product Highlights Section ................. 1 Changes to Table 3 ............................................................................ 5 Changes to Table 2 ............................................................................. 4 Changes to Table 9 .......................................................................... 11 Added AD5679/AD5679R Specifications Section and Table 2 Changes to Figure 9 ........................................................................ 12 Renumbered Sequentially ................................................................ 6 Changes to Figure 13 to Figure 18 ................................................ 13 Changes to Thermal Resistance Section ..................................... 11 Changes to Figure 19 to Figure 24 ................................................ 14 Changes to Figure 7 to Figure 12.................................................. 12 Changes to Figure 25 to Figure 30 ................................................ 15 Changes to Figure 13 to Figure 18 ............................................... 13 Changes to Figure 31 and Figure 32............................................. 16 Changes to Figure 19 to Figure 24 ............................................... 14 Changes to Hardware Reset (RESET) Section and Figure 52 and Changes to Figure 25 to Figure 30 ............................................... 15 Changes to Figure 31 to Figure 36 ............................................... 16 Figure 53, Moved Table 19............................................................. 19 Changes to Figure 37 to Figure 42 ............................................... 17 Added Figure 60 and Changes to Internal Reference Section .. 24 Changes to Figure 60...................................................................... 25 LDAC Instantaneous DAC Updating ( Held Low) and Deferred Added Long-Term Temperature Drift Section and Figure 64 LDAC DAC Updating ( is Pulsed Low) Sections ........................ 28 Renumbered Sequentially ............................................................. 28 RESET Hardware Reset ( ) Section ................................................ 29 Changes to Figure 67 and Figure 68 ............................................ 30 Changes to Ordering Guide .......................................................... 32 Changes to Ordering Guide .......................................................... 32 11/2019Rev. 0 to Rev. A 8/2019Revision 0: Initial Version Added AD5674, AD5674R, and AD5679................... Throughout Rev. B Page 2 of 32