Octal, 16-Bit nanoDAC+ 2 with I C Interface Data Sheet AD5675 FEATURES GENERAL DESCRIPTION High performance The AD5675 is a low power, octal, 16-bit buffered voltage output High relative accuracy (INL): 3 LSB maximum at 16 bits digital-to-analog converter (DAC). The device includes a gain Total unadjusted error (TUE): 0.14% of FSR maximum select pin, giving a full-scale output of VREF (gain = 1) or 2 Offset error: 1.5 mV maximum VREF (gain = 2). The device operates from a single 2.7 V to 5.5 V Gain error: 0.06% of FSR maximum supply and is guaranteed monotonic by design. The AD5675 is Wide operating ranges available in 20-lead TSSOP and LFCSP packages. The power-on 40C to +125C temperature range reset circuit and a RSTSEL pin ensure that the output DACs power 2.7 V to 5.5 V power supply up to zero scale or midscale and remain there until a valid write Easy implementation takes place. The AD5675 contains a power-down mode, reducing User selectable gain of 1 or 2 (GAIN pin/bit) the current consumption to 1 A typical while in power-down 1.8 V logic compatibility mode. The AD5675 uses a versatile 2-wire serial interface that 2 I C-compatible serial interface operates at clock rates up to 400 kHz, and includes a VLOGIC pin 20-lead TSSOP and LFCSP RoHS-compliant packages intended for 1.62 V to 5.5 V logic. APPLICATIONS Table 1. Octal nanoDAC+ Devices Optical transceivers Interface Reference 16-Bit 12-Bit Base station power amplifiers SPI Internal AD5676R AD5672R Process control (PLC input/output cards) External AD5676 Not applicable Industrial automation 2 I C Internal AD5675R AD5671R Data acquisition systems FUNCTIONAL BLOCK DIAGRAM V V V LOGIC DD REF AD5675 BUFFER DAC INPUT STRING V 0 OUT REGISTER REGISTER DAC 0 BUFFER DAC STRING INPUT V 1 OUT REGISTER REGISTER DAC 1 BUFFER DAC STRING INPUT SCL V 2 OUT REGISTER REGISTER DAC 2 BUFFER DAC INPUT STRING SDA V 3 OUT REGISTER DAC 3 REGISTER BUFFER DAC INPUT STRING A1 V 4 OUT REGISTER DAC 4 REGISTER BUFFER DAC A0 INPUT STRING V 5 OUT REGISTER REGISTER DAC 5 BUFFER DAC STRING INPUT V 6 LDAC REGISTER REGISTER DAC 6 OUT BUFFER DAC STRING INPUT V 7 RESET REGISTER REGISTER DAC 7 OUT GAIN POWER-DOWN POWER-ON 1/2 LOGIC RESET RSTSEL GAIN GND Figure 1. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20152018 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com INTERFACE LOGIC 12550-001AD5675 Data Sheet TABLE OF CONTENTS 2 Features .............................................................................................. 1 I C Slave Address ........................................................................ 20 Applications ....................................................................................... 1 Serial Operation ......................................................................... 20 General Description ......................................................................... 1 Write Operation.......................................................................... 20 Functional Block Diagram .............................................................. 1 Read Operation........................................................................... 21 Revision History ............................................................................... 2 Multiple DAC Readback Sequence .......................................... 21 Specifications ..................................................................................... 3 Power-Down Operation ............................................................ 22 AC Characteristics ........................................................................ 5 LDAC Load DAC (Hardware Pin) ........................................... 22 Timing Characteristics ................................................................ 5 LDAC Mask Register ................................................................. 23 Absolute Maximum Ratings ............................................................ 7 Hardware Reset (RESET) .......................................................... 24 Thermal Resistance ...................................................................... 7 Reset Select Pin (RSTSEL) ........................................................ 24 ESD Caution .................................................................................. 7 Software Reset ............................................................................. 24 Pin Configuration and Function Descriptions ............................. 8 Amplifier Gain Selection on LFCSP Package ......................... 24 Typical Performance Characteristics ........................................... 10 Applications Information .............................................................. 25 Terminology .................................................................................... 16 Power Supply Recommendations ............................................. 25 Theory of Operation ...................................................................... 18 Microprocessor Interfacing ....................................................... 25 Digital-to-Analog Converter .................................................... 18 AD5675 to ADSP-BF531 Interface ........................................... 25 Transfer Function ....................................................................... 18 Layout Guidelines....................................................................... 25 DAC Architecture ....................................................................... 18 Galvanically Isolated Interface ................................................. 25 Serial Interface ............................................................................ 19 Outline Dimensions ....................................................................... 26 Write and Update Commands .................................................. 20 Ordering Guide .......................................................................... 27 REVISION HISTORY 4/2018Rev. B to Rev. C 8/2016Rev. A to Rev. B Changes to Features Section, General Description Section, and Change to Output Noise Spectral Density Parameter Table 3 ... 5 Figure 1 .............................................................................................. 1 Changes to Specifications Section .................................................. 3 10/2015Rev. 0 to Rev. A Changes to VLOGIC Parameter, Table 2 ............................................ 4 Added 20-Lead LFCSP ...................................................... Universal Deleted Endnote 3, Table 2 Renumbered Sequentially .............. 4 Changes to Features Section and General Description Section .... 1 Changes to AC Characteristics Section, Timing Characteristics Changes to Table 2 ............................................................................. 3 Section, and Table 3 .......................................................................... 5 Change to Table 5 .............................................................................. 7 Changes to Figure 2 and Figure 3 ................................................... 6 Added Table 6 Renumbered Sequentially ..................................... 9 Changes to Table 5 and Thermal Resistance Section ................... 7 Change to Figure 4 Caption and Table 6 Title ............................... 8 Change to VLOGIC Pin Description, Table 7 .................................... 8 Added Figure 5 Renumbered Sequentially and Table 7 .............. 9 Change to VLOGIC Pin Description, Table 8 .................................... 9 Change to Figure 19 Caption ........................................................ 12 Changes to Figure 19 ...................................................................... 12 Change to Figure 33 ....................................................................... 14 Changes to Table 9 .......................................................................... 19 Change to Table 8 ........................................................................... 19 Changes to Update DAC Register n with Contents of Input Change to Read Operation Section .............................................. 21 Register n Section and Write to and Update DAC Channel n Changes to LDAC Mask Register Section and Table 13 ............... 23 (Independent of LDAC) Section................................................... 20 Added Amplifier Gain Selection on LFCSP Package Section, Changes to Power-Down Operation Section .............................. 22 Table 15, and Table 16 .................................................................... 24 Changes to Hardware Reset (RESET) Section ............................ 24 Added Figure 52, Outline Dimensions ........................................ 26 Added Software Reset Section ...................................................... 24 Changes to Ordering Guide .......................................................... 26 Updated Outline Dimensions ....................................................... 26 Changes to Ordering Guide .......................................................... 27 1/2015Revision 0: Initial Version Rev. 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