Octal, 16-Bit nanoDAC+ with SPI Interface Data Sheet AD5676 FEATURES GENERAL DESCRIPTION High performance The AD5676 is a low power, octal, 16-bit buffered voltage High relative accuracy (INL): 3 LSB maximum at 16 bits output digital-to-analog converter (DAC). The device includes Total unadjusted error (TUE): 0.14% of FSR maximum a gain select pin, giving a full-scale output of VREF (gain = 1) or Offset error: 1.5 mV maximum 2 VREF (gain = 2). The AD5676 DAC operates from a single Gain error: 0.06% of FSR maximum 2.7 V to 5.5 V supply and is guaranteed monotonic by design. Wide operating ranges The AD5676 is available in 20-lead TSSOP and LFCSP packages. 40C to +125C temperature range The internal power-on reset circuit and the RSTSEL pin of the 2.7 V to 5.5 V power supply AD5676 ensure that the output DACs power up to zero scale or Easy implementation midscale and then remain there until a valid write takes place. The User selectable gain of 1 or 2 (GAIN pin/gain bit) AD5676 contains a per channel power-down mode that typically Reset to zero scale or midscale (RSTSEL pin) reduces the current consumption of the device to 1 A. 1.8 V logic compatibility The AD5676 employs a versatile serial peripheral interface (SPI) 50 MHz SPI with readback or daisy chain that operates at clock rates up to 50 MHz, and contains a V pin LOGIC 20-lead, TSSOP and LFCSP RoHS-compliant packages intended for 1.62 V to 5.5 V logic. APPLICATIONS Table 1. Octal nanoDAC+ Devices Optical transceivers Interface Reference 16-Bit 12-Bit Base station power amplifiers SPI Internal AD5676R AD5672R Process control (PLC input/output cards) External AD5676 Not applicable Industrial automation 2 I C Internal AD5675R AD5671R Data acquisition systems External AD5675 Not applicable PRODUCT HIGHLIGHTS 1. High relative accuracy (INL) 16-bit: 3 LSB maximum. 2. 40C to +125C temperature range. 3. 20-lead, TSSOP and LFCSP RoHS-compliant packages. FUNCTIONAL BLOCK DIAGRAM V V V LOGIC DD REF AD5676 BUFFER INPUT DAC STRING V 0 OUT REGISTER REGISTER DAC 0 BUFFER INPUT DAC STRING V 1 OUT REGISTER REGISTER DAC 1 BUFFER INPUT DAC STRING SCLK V 2 OUT REGISTER REGISTER DAC 2 BUFFER INPUT DAC STRING SYNC V 3 OUT REGISTER REGISTER DAC 3 INTERFACE LOGIC BUFFER INPUT DAC STRING SDI V 4 OUT REGISTER REGISTER DAC 4 BUFFER INPUT DAC STRING SDO V 5 OUT REGISTER REGISTER DAC 5 BUFFER INPUT DAC STRING LDAC V 6 OUT REGISTER REGISTER DAC 6 BUFFER INPUT DAC STRING RESET V 7 OUT REGISTER REGISTER DAC 7 POWER-DOWN POWER-ON RESET GAIN x1/x2 LOGIC RSTSEL GAIN GND Figure 1. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20142018 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com 12549-001AD5676 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Standalone Operation ................................................................ 23 Applications ....................................................................................... 1 Write and Update Commands .................................................. 23 General Description ......................................................................... 1 Daisy-Chain Operation ............................................................. 23 Product Highlights ........................................................................... 1 Readback Operation .................................................................. 24 Functional Block Diagram .............................................................. 1 Power-Down Operation ............................................................ 24 Revision History ............................................................................... 2 LDAC Load DAC (Hardware Pin) ........................................... 25 Specifications ..................................................................................... 4 LDAC Mask Register ................................................................. 25 AC Characteristics ........................................................................ 6 Hardware Reset ( ) .......................................................... 26 RESET Timing Characteristics ................................................................ 7 Reset Select Pin (RSTSEL) ........................................................ 26 Daisy-Chain and Readback Timing Characteristics................ 8 Software Reset ............................................................................. 26 Absolute Maximum Ratings .......................................................... 10 Amplifier Gain Selection on LFCSP Package ......................... 26 Thermal Resistance .................................................................... 10 Applications Information .............................................................. 27 ESD Caution ................................................................................ 10 Power Supply Recommendations ............................................. 27 Pin Configurations and Function Descriptions ......................... 11 Microprocessor Interfacing ....................................................... 27 Typical Performance Characteristics ........................................... 13 AD5676 to ADSP-BF531 Interface .......................................... 27 Terminology .................................................................................... 19 AD5676 to SPORT Interface ..................................................... 27 Theory of Operation ...................................................................... 21 Layout Guidelines....................................................................... 27 Digital-to-Analog Converter .................................................... 21 Galvanically Isolated Interface ................................................. 28 Transfer Function ....................................................................... 21 Outline Dimensions ....................................................................... 29 DAC Architecture ....................................................................... 21 Ordering Guide .......................................................................... 29 Serial Interface ............................................................................ 22 REVISION HISTORY 5/2018Rev. C to Rev. D Changes to Update DAC Register with Contents of Input Register n Change to to SCLK Falling Edge Parameter, Table 5 ....... 8 SYNC Section and Write to and Update DAC Channel n (Independent of LDAC) Section ........................................................................... 23 Changes to Readback Operation Section and Power-Down 4/2018Rev. B to Rev. C Operation Section........................................................................... 24 Changes to Features Section and General Description Section ....... 1 RESET Changes to Specifications Section .................................................. 4 Changes to Hardware Reset ( ) Section ............................ 26 Added Software Reset Section ...................................................... 26 Changes to VLOGIC Parameter, Table 2 ............................................ 5 Updated Outline Dimensions ....................................................... 29 Deleted Endnote 3, Table 2 Renumbered Sequentially .............. 5 Changes to AC Characteristics Section and Output Noise Spectral Density (NSD) Parameter, Table 3 .................................. 6 10/2015Rev. A to Rev. B Changes to Timing Characteristics Section, Table 4, and Added 20-Lead LFCSP ...................................................... Universal Figure 2 .............................................................................................. 7 Changes to Features Section, General Description Section, Changes to Daisy-Chain and Readback Timing Characteristics Table 1, Product Highlights Section, and Figure 1 ....................... 1 Changes to Table 2 ............................................................................. 3 Section, Table 5, Figure 3, and Figure 4 ......................................... 8 Deleted Figure 5 Renumbered Sequentially ................................. 8 Added Figure 5 Renumbered Sequentially .................................. 9 Change to Table 5 .............................................................................. 8 Deleted ESD Ratings Parameter, Table 6 ..................................... 10 Added Table 6 Renumbered Sequentially ..................................... 8 Changes to Thermal Resistance Section ...................................... 10 Change to VLOGIC Pin Description, Table 8 .................................. 11 Change to Table 7 .............................................................................. 9 Change to V Pin Description, Table 9 .................................. 12 Added Figure 6 and Table 8 .......................................................... 10 LOGIC Changes to Figure 21 ...................................................................... 15 Change to Figure 10 to Figure 12 ................................................. 11 Changes to Table 10 ........................................................................ 22 Change to Figure 13 to Figure 18 ................................................. 12 Deleted Endnote 1, Table 11.......................................................... 22 Changes to Figure 19, Figure 20, and Figure 22 ......................... 13 Rev. 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