16-Channel, 12-/16-Bit nanoDAC+ with 2 2 ppm/C Voltage Reference TC, I C Interface Data Sheet AD5673R/AD5677R FEATURES GENERAL DESCRIPTION High performance The AD5673R/AD5677R are low power, 16-channel, 12-/16-bit, High relative accuracy (INL): 4 LSB maximum at 16 bits buffered voltage output, digital-to-analog converters (DACs) (AD5677R only) that include a 2.5 V, 2 ppm/C internal reference (enabled by TUE: 0.14% of FSR maximum default), and a gain select pin, resulting in a full-scale output of Offset error: 1.5 mV maximum 2.5 V (gain = 1) or 5 V (gain = 2). The devices operate from a Gain error: 0.06% of FSR maximum single, 2.7 V to 5.5 V supply range and are guaranteed monotonic Low drift, 2.5 V voltage reference TC: 2 ppm/C typical by design. The AD5673R/AD5677R are available in a 28-lead lead 40 mA short-circuit current frame chip scale package (LFCSP) and incorporate a power-on Wide operating ranges reset (POR) circuit that ensures that the DAC outputs power up 40C to +125C temperature range to and remain at zero scale or midscale until a valid write. The 2.7 V to 5.5 V power supply range AD5673R/AD5677R contain a power-down mode that reduces Simplified implementation the current consumption to 2 A typical. User selectable gain of 1 or 2 (GAIN pin) Table 1. Octal and 16-Channel nanoDAC+ Devices 1.8 V logic compatibility 2 Channel 400 kHz I C-compatible serial interface Count Interface Reference 16-Bit 12-Bit 28-lead, 4 mm 4 mm, RoHS compliant LFCSP 8 SPI Internal AD5676R AD5672R APPLICATIONS External AD5676 Not applicable 2 I C Internal AD5675R AD5671R Optical transceivers 16 SPI Internal AD5679R AD5674R Base station power amplifiers External AD5679 AD5674 Process control (programmable logic controller (PLC) 2 I C Internal AD5677R AD5673R input/output cards) Industrial automation PRODUCT HIGHLIGHTS Data acquisition systems 1. High channel density: 16 channels in 4 mm 4 mm LFCSP. 2. High relative accuracy (INL). AD5673R (12-bit): 1 LSB maximum. AD5677R (16-bit): 4 LSB maximum. 3. Low drift, 2.5 V, on-chip reference. FUNCTIONAL BLOCK DIAGRAM VLOGIC VDD VREF AD5673R/AD5677R 2.5V REF BUFFER INPUT DAC STRING VOUT0 REGISTER REGISTER DAC 0 SCL SDA A1 BUFFER A0 INPUT DAC STRING VOUT14 REGISTER REGISTER DAC 14 BUFFER INPUT DAC STRING LDAC VOUT15 REGISTER REGISTER DAC 15 RESET POWER-ON GAIN POWER-DOWN RESET 1/2 LOGIC GAIN GND Figure 1. Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 2020 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com INTERFACE LOGIC 22962-001AD5673R/AD5677R Data Sheet TABLE OF CONTENTS 2 Features .............................................................................................. 1 I C Slave Address ........................................................................ 25 Applications ....................................................................................... 1 Serial Operation ......................................................................... 25 General Description ......................................................................... 1 Write Operation.......................................................................... 25 Product Highlights ........................................................................... 1 Read Operation........................................................................... 25 Functional Block Diagram .............................................................. 1 Multiple DAC Readback Sequence .......................................... 25 Revision History ............................................................................... 2 Power-Down Operation ............................................................ 27 Specifications ..................................................................................... 3 LDAC Load DAC (Hardware Pin) ........................................... 27 AD5673R Specifications .............................................................. 3 LDAC Mask Register ................................................................. 28 AD5677R Specifications .............................................................. 5 Hardware Reset (RESET) .......................................................... 28 AC Characteristics ........................................................................ 7 Power-On Reset Internal Circuit.............................................. 28 Timing Characteristics ................................................................ 8 Software Reset ............................................................................. 28 Absolute Maximum Ratings ............................................................ 9 Internal Reference Setup ........................................................... 28 Thermal Resistance ...................................................................... 9 Solder Heat Reflow ..................................................................... 29 ESD Caution .................................................................................. 9 Long-Term Temperature Drift ................................................. 29 Pin Configuration and Function Descriptions ........................... 10 Thermal Hysteresis .................................................................... 29 Typical Performance Characteristics ........................................... 12 Applications Information .............................................................. 30 Terminology .................................................................................... 21 Power Supply Recommendations ............................................. 30 Theory of Operation ...................................................................... 23 Microprocessor Interfacing ....................................................... 30 Digital-to-Analog Converter (DAC) ....................................... 23 AD5673R/AD5677R to ADSP-BF531 Interface ..................... 30 Transfer Function ....................................................................... 23 Layout Guidelines....................................................................... 30 DAC Architecture ....................................................................... 23 Galvanically Isolated Interface ................................................. 30 Serial Interface ............................................................................ 23 Outline Dimensions ....................................................................... 31 Write and Update Commands .................................................. 25 Ordering Guide .......................................................................... 31 REVISION HISTORY 4/2020Revision 0: Initial Version Rev. 0 Page 2 of 31