4 12-Bit and 4 16-Bit Octal DAC with On-Chip Reference in 14-Lead TSSOP AD5678 FEATURES FUNCTIONAL BLOCK DIAGRAM V /V V REFIN REFOUT DD Low power octal DAC with AD5678 1.25V/2.5V Four 16-bit DACs REF BUFFER Four 12-bit DACs INPUT DAC STRING V A LDAC OUT REGISTER REGISTER DAC A 14-lead/16-lead TSSOP BUFFER INPUT DAC STRING V B OUT REGISTER DAC B REGISTER On-chip 1.25 V/2.5 V, 5 ppm/C reference BUFFER DAC INPUT STRING SCLK V C OUT Power down to 400 nA 5 V, 200 nA 3 V REGISTER REGISTER DAC C INTERFACE BUFFER 2.7 V to 5.5 V power supply INPUT DAC STRING SYNC LOGIC V D OUT REGISTER REGISTER DAC D Guaranteed monotonic by design BUFFER INPUT DAC STRING DIN V E OUT REGISTER REGISTER DAC E Power-on reset to zero scale BUFFER INPUT DAC STRING V F REGISTER OUT 3 power-down functions REGISTER DAC F BUFFER DAC Hardware LDAC and LDAC override function INPUT STRING V G OUT REGISTER REGISTER DAC G CLR function to programmable code BUFFER INPUT DAC STRING V H OUT REGISTER REGISTER DAC H Rail-to-rail operation POWER-DOWN POWER-ON LOGIC RESET 1 GND LDAC 1 CLR APPLICATIONS 1 RU-16 PACKAGE ONLY Figure 1. Process control Data acquisition systems Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage current sources Programmable attenuators GENERAL DESCRIPTION The AD5678 is a low power, octal, buffered voltage-output The outputs of all DACs can be updated simultaneously using the function, with the added functionality of user- DAC with four 12-bit DACs and four 16-bit DACs in a single LDAC package. All devices operate from a single 2.7 V to 5.5 V supply selectable DAC channels to simultaneously update. There is and are guaranteed monotonic by design. also an asynchronous that clears all DACs to a software- CLR selectable code0 V, midscale, or full scale. The AD5678 has an on-chip reference with an internal gain of 2. The AD5678-1 has a 1.25 V 5 ppm/C reference, giving a full- The AD5678 utilizes a versatile 3-wire serial interface that scale output of 2.5 V the AD5678-2 has a 2.5 V 5 ppm/C operates at clock rates of up to 50 MHz and is compatible with reference, giving a full-scale output of 5 V. The on-board standard SPI, QSPI, MICROWIRE, and DSP interface reference is off at power-up, allowing the use of an external standards. The on-chip precision output amplifier enables rail- reference. The internal reference is enabled via a software write. to-rail output swing. The part incorporates a power-on reset circuit that ensures that PRODUCT HIGHLIGHTS the DAC output powers up to 0 V and remains powered up at 1. Octal DAC (four 12-bit DACs and four 16-bit DACs). this level until a valid write takes place. The part contains a 2. On-chip 1.25 V/2.5 V, 5 ppm/C reference. power-down feature that reduces the current consumption of 3. Available in 14-lead/16-lead TSSOP. the device to 400 nA at 5 V and provides software-selectable 4. Power-on reset to 0 V. output loads while in power-down mode for any or all DAC 5. Power-down capability. When powered down, the DAC channels. typically consumes 200 nA at 3 V and 400 nA at 5 V. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 20052011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 05299-001AD5678 TABLE OF CONTENTS Features .............................................................................................. 1 D/A Section................................................................................. 20 Applications....................................................................................... 1 Resistor String............................................................................. 20 Functional Block Diagram .............................................................. 1 Internal Reference ...................................................................... 20 General Description ......................................................................... 1 Output Amplifier........................................................................ 21 Product Highlights ........................................................................... 1 Serial Interface ............................................................................ 21 Revision History ............................................................................... 2 Input Shift Register .................................................................... 22 Specifications..................................................................................... 3 Interrupt .......................................................................... 22 SYNC AC Characteristics........................................................................ 7 Internal Reference Register....................................................... 23 Timing Characteristics ................................................................ 8 Power-On Reset.......................................................................... 23 Absolute Maximum Ratings............................................................ 9 Power-Down Modes .................................................................. 23 ESD Caution.................................................................................. 9 Clear Code Register ................................................................... 23 Pin Configuration and Function Descriptions........................... 10 Function .......................................................................... 25 LDAC Typical Performance Characteristics ........................................... 11 Power Supply Bypassing and Grounding................................ 25 Terminology .................................................................................... 18 Outline Dimensions....................................................................... 26 Theory of Operation ...................................................................... 20 Ordering Guide .......................................................................... 26 REVISION HISTORY 2/11Rev. B to Rev. C Changes to Zero-Code Error Parameter and Offset Error Parameter, Table 1............................................................................. 3 Changes to Zero-Code Error Parameter and Offset Error Parameter, Table 2............................................................................. 5 2/09Rev. A to Rev. B Changes to Reference Current Parameter, Table 1....................... 3 Change to IDD (Normal Mode) Parameter, Table 1 ...................... 4 Changes to Reference Current Parameter, Table 2....................... 5 Change to IDD (Normal Mode) Parameter, Table 2 ...................... 6 11/05Rev. 0 to Rev. A Change to General Description ...................................................... 1 Change to Specifications.................................................................. 3 Replaced Figure 48 ......................................................................... 22 Change to the Power-Down Modes Section ............................... 23 10/05Revision 0: Initial Version Rev. C Page 2 of 28