Quad, 16-/14-/12-Bit nanoDAC+ with 2 ppm/C Reference, SPI Interface Data Sheet AD5686R/AD5685R/AD5684R FEATURES FUNCTIONAL BLOCK DIAGRAM V GND V DD REF High relative accuracy (INL): 2 LSB maximum at 16 bits Low drift 2.5 V reference: 2 ppm/C typical AD5686R/AD5685R/AD5684R 2.5V REFERENCE Tiny package: 3 mm 3 mm, 16-lead LFCSP V LOGIC INPUT DAC STRING Total unadjusted error (TUE): 0.1% of FSR maximum V A OUT DAC A REGISTER REGISTER SCLK BUFFER Offset error: 1.5 mV maximum Gain error: 0.1% of FSR maximum INPUT DAC STRING V B OUT REGISTER REGISTER DAC B SYNC High drive capability: 20 mA, 0.5 V from supply rails BUFFER User selectable gain of 1 or 2 (GAIN pin) STRING INPUT DAC SDIN V C OUT REGISTER REGISTER DAC C Reset to zero scale or midscale (RSTSEL pin) BUFFER 1.8 V logic compatibility SDO STRING INPUT DAC V D OUT REGISTER REGISTER DAC D 50 MHz SPI with readback or daisy chain BUFFER Low glitch: 0.5 nV-sec POWER-ON GAIN POWER- RESET 1/2 DOWN Low power: 3.3 mW at 3 V LOGIC 2.7 V to 5.5 V power supply LDAC RESET RSTSEL GAIN 40C to +105C temperature range Figure 1. APPLICATIONS Optical transceivers Base-station power amplifiers Process control (PLC I/O cards) Industrial automation Data acquisition systems GENERAL DESCRIPTION The AD5686R/AD5685R/AD5684R, members of the Table 1. Quad nanoDAC+ Devices nanoDAC+ family, are low power, quad, 16-/14-/12-bit Interface Reference 16-Bit 14-Bit 12-Bit buffered voltage output DACs. The devices include a 2.5 V, SPI Internal AD5686R AD5685R AD5684R 2 ppm/C internal reference (enabled by default) and a gain External AD5686 AD5684 select pin giving a full-scale output of 2.5 V (gain = 1) or 5 V 2 I C Internal AD5696R AD5695R AD5694R (gain = 2). All devices operate from a single 2.7 V to 5.5 V External AD5696 AD5694 supply, are guaranteed monotonic by design, and exhibit less than 0.1% FSR gain error and 1.5 mV offset error performance. PRODUCT HIGHLIGHTS The devices are available in a 3 mm 3 mm LFCSP and a 1. High Relative Accuracy (INL). TSSOP package. AD5686R (16-bit): 2 LSB maximum The AD5686R/AD5685R/AD5684R also incorporate a power- AD5685R (14-bit): 1 LSB maximum on reset circuit and a RSTSEL pin that ensures that the DAC AD5684R (12-bit): 1 LSB maximum outputs power up to zero scale or midscale and remains there 2. Low Drift 2.5 V On-Chip Reference. until a valid write takes place. Each part contains a per-channel 2 ppm/C typical temperature coefficient power-down feature that reduces the current consumption of 5 ppm/C maximum temperature coefficient the device to 4 A at 3 V while in power-down mode. 3. Two Package Options. The AD5686R/AD5685R/AD5684R employ a versatile SPI 3 mm 3 mm, 16-lead LFCSP interface that operates at clock rates up to 50 MHz, and all 16-lead TSSOP devices contain a VLOGIC pin intended for 1.8 V/3 V/5 V logic. Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. Tel: 781.329.4700 20122020 Analog Devices, Inc. All rights reserved. No license is granted by implication or otherwise under any patent or patent rights of Analog Technical Support www.analog.com Devices. Trademarks and registered trademarks are the property of their respective owners. INTERFACE LOGIC 10485-001AD5686R/AD5685R/AD5684R Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Write and Update Commands ................................................. 22 Applications ...................................................................................... 1 Daisy-Chain Operation ............................................................. 23 Functional Block Diagram .............................................................. 1 Readback Operation .................................................................. 23 General Description ......................................................................... 1 Power-Down Operation ............................................................ 24 Product Highlights ........................................................................... 1 LDAC Load DAC (Hardware Pin) .......................................... 25 Revision History ............................................................................... 2 LDAC Mask Register ................................................................. 25 Specifications .................................................................................... 3 Hardware Reset ( ) .......................................................... 26 RESET AC Characteristics ....................................................................... 5 Reset Select Pin (RSTSEL) ........................................................ 26 Timing Characteristics ................................................................ 6 Internal Reference Setup ........................................................... 26 Daisy-Chain and Readback Timing Characteristics ............... 7 Solder Heat Reflow .................................................................... 26 Absolute Maximum Ratings ........................................................... 9 Thermal Hysteresis .................................................................... 27 ESD Caution.................................................................................. 9 Long-Term Temperature Drift ................................................ 27 Pin Configuration and Function Descriptions .......................... 10 Applications Information ............................................................. 28 Typical Performance Characteristics ........................................... 11 Microprocessor Interfacing ...................................................... 28 Terminology .................................................................................... 18 AD5686R/AD5685R/AD5684R to ADSP-BF531 Interface . 28 Theory of Operation ...................................................................... 20 AD5686R/AD5685R/AD5684R to SPORT Interface ............ 28 Digital-to-Analog Converter .................................................... 20 Layout Guidelines ...................................................................... 28 Transfer Function ...................................................................... 20 Galvanically Isolated Interface ................................................. 29 DAC Architecture ...................................................................... 20 Outline Dimensions ....................................................................... 30 Serial Interface ............................................................................ 21 Ordering Guide .......................................................................... 31 Standalone Operation ................................................................ 22 REVISION HISTORY 8/2020Rev. D to Rev. E Changes to Hardware Reset (RESET) Section ........................... 26 Changes to Readback Operation Section .................................... 23 Added Long-Term Temperature Drift Section and LDAC Changes to Mask Register Section ................................... 25 Figure 58 .......................................................................................... 27 RESET Changes to Hardware Reset ( ) Section ........................... 26 5/2014Rev. B to Rev. C. Updated Outline Dimensions ....................................................... 30 Deleted Long-Term Stability/Drift Parameter, Table 1 ............... 4 Changes to Ordering Guide .......................................................... 31 Deleted Figure 11 Renumbered Sequentially ............................ 11 Deleted Long-Term Temperature Drift Section and Figure 58 1/2017Rev. C to Rev. D Renumbered Sequentially ............................................................. 26 Changes to Features Section ........................................................... 1 Changes to VLOGIC Parameter, Table 2 ........................................... 4 6/2013Rev. A to Rev. B Changes to Output Noise Spectral Density Parameter, Changes to Pin GAIN and Pin RSTSEL Descriptions Table 6 .. 10 Table 3 ................................................................................................ 5 Changes to Table 4 and Figure 2 .................................................... 6 9/2012Rev. 0 to Rev. A Changes to Table 5 and Figure 4 .................................................... 7 Changes to Table 1 ............................................................................ 1 Changes to Figure 5 .......................................................................... 8 Changes to Figure 13 ..................................................................... 11 Changes to Table 6 ........................................................................... 9 Changes to Figure 36 ..................................................................... 15 Changes to RESET Pin Description, Table 7 .............................. 10 Changes to Table 8 ......................................................................... 21 4/2012Revision 0: Initial Version Changes to Readback Operation Section .................................... 23 Rev. E Page 2 of 31