Quad, 16-/12-Bit nanoDAC+ with SPI Interface Data Sheet AD5686/AD5684 FEATURES FUNCTIONAL BLOCK DIAGRAM V GND V DD REF High relative accuracy (INL): 2 LSB maximum 16 bits Tiny package: 3 mm 3 mm, 16-lead LFCSP AD5686/AD5684 Total unadjusted error (TUE): 0.1% of FSR maximum V LOGIC INPUT DAC STRING Offset error: 1.5 mV maximum V A OUT REGISTER REGISTER DAC A SCLK BUFFER Gain error: 0.1% of FSR maximum INPUT DAC STRING High drive capability: 20 mA, 0.5 V from supply rails V B OUT DAC B REGISTER REGISTER SYNC BUFFER User selectable gain of 1 or 2 (GAIN pin) STRING Reset to zero scale or midscale (RSTSEL pin) INPUT DAC SDIN V C OUT DAC C REGISTER REGISTER 1.8 V logic compatibility BUFFER SDO 50 MHz SPI with readback or daisy chain STRING INPUT DAC V D OUT REGISTER REGISTER DAC D Low glitch: 0.5 nV-sec BUFFER Low power: 1.8 mW at 3 V POWER-ON GAIN POWER- RESET 1/2 DOWN LOGIC 2.7 V to 5.5 V power supply 40C to +105C temperature range LDAC RESET RSTSEL GAIN Figure 1. APPLICATIONS Digital gain and offset adjustment Programmable attenuators Process control (PLC I/O cards) Industrial automation Data acquisition systems GENERAL DESCRIPTION The AD5686/AD5684, members of the nanoDAC+ family, are Table 1. Quad nanoDAC+ Devices low power, quad, 16-/12-bit buffered voltage output DACs. Interface Reference 16-Bit 14-Bit 12-Bit The devices include a gain select pin giving a full-scale output SPI Internal AD5686R AD5685R AD5684R of 2.5 V (gain = 1) or 5 V (gain = 2). All devices operate from SPI External AD5686 AD5684 a single 2.7 V to 5.5 V supply, are guaranteed monotonic by 2 I C Internal AD5696R AD5695R AD5694R design, and exhibit less than 0.1% FSR gain error and 1.5 mV 2 I C External AD5696 AD5694 offset error performance. The devices are available in a 3 mm 3 mm LFCSP and a TSSOP package. PRODUCT HIGHLIGHTS The AD5686/AD5684 also incorporate a power-on reset circuit 1. High Relative Accuracy (INL). and a RSTSEL pin that ensures that the DAC outputs power up AD5686 (16-bit): 2 LSB maximum to zero scale or midscale and remain at that level until a valid AD5684 (12-bit): 1 LSB maximum write takes place. Each part contains a per-channel power-down 2. Excellent DC Performance. feature that reduces the current consumption of the device to Total unadjusted error: 0.1% of FSR maximum 4 A at 3 V while in power-down mode. Offset error: 1.5 mV maximum The AD5686/AD5684 employ a versatile SPI interface that Gain error: 0.1% of FSR maximum operates at clock rates up to 50 MHz, and all devices contain 3. Two Package Options. a VLOGIC pin intended for 1.8 V/3 V/5 V logic. 3 mm 3 mm, 16-lead LFCSP 16-lead TSSOP Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20122017 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com INTERFACE LOGIC 10797-001AD5686/AD5684 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Serial Interface ............................................................................ 19 Applications ....................................................................................... 1 Standalone Operation ................................................................ 20 Functional Block Diagram .............................................................. 1 Write and Update Commands .................................................. 20 General Description ......................................................................... 1 Daisy-Chain Operation ............................................................. 20 Product Highlights ........................................................................... 1 Readback Operation .................................................................. 21 Revision History ............................................................................... 2 Power-Down Operation ............................................................ 21 Specifications ..................................................................................... 3 LDAC Load DAC (Hardware Pin) ........................................... 22 AC Characteristics ........................................................................ 5 LDAC Mask Register ................................................................. 22 Timing Characteristics ................................................................ 6 Hardware Reset (RESET) .......................................................... 23 Daisy-Chain and Readback Timing Characteristics................ 7 Reset Select Pin (RSTSEL) ........................................................ 23 Absolute Maximum Ratings ............................................................ 9 Applications Information .............................................................. 24 ESD Caution .................................................................................. 9 Microprocessor Interfacing ....................................................... 24 Pin Configurations and Function Descriptions ......................... 10 AD5686/AD5684 to ADSP-BF531 Interface .......................... 24 Typical Performance Characteristics ........................................... 11 AD5686/AD5684 to SPORT Interface .................................... 24 Terminology .................................................................................... 16 Layout Guidelines....................................................................... 24 Theory of Operation ...................................................................... 18 Galvanically Isolated Interface ................................................. 25 Digital-to-Analog Converter .................................................... 18 Outline Dimensions ....................................................................... 26 Transfer Function ....................................................................... 18 Ordering Guide .......................................................................... 27 DAC Architecture ....................................................................... 18 REVISION HISTORY 6/2017Rev. B to Rev. C 3/2015Rev. A to Rev. B Changes to Features Section 1 ........................................................ 1 Changes to Table 4 and Figure 2 ...................................................... 6 Changes to Table 2 ............................................................................ 3 Inserted Note 2 to Ordering Guide .............................................. 27 Changes to Table 3 ............................................................................ 5 Changes to Table 4 ............................................................................ 6 6/2013Rev. 0 to Rev. A Changes to Table 5 and Figure 4 ..................................................... 7 Changes to Pin GAIN and Pin RSTSEL Descriptions Table 7 .. 10 Changes to Figure 5 .......................................................................... 8 Changes to Table 6 ............................................................................ 9 7/2012Revision 0: Initial Version Change to V Pin Description and RESET Pin Description, LOGIC Table 7 ................................................................................................ 9 Changes to Figure 12 and Figure 13 ............................................. 11 Changes to Figure 14 to Figure 19 ................................................ 12 Changes to Figure 20, Figure 22, and Figure 25 ......................... 13 Changes to Figure 32 ...................................................................... 15 Changes to Table 8 .......................................................................... 19 Changes to Readback Operation Section .................................... 21 Changes to Hardware Reset (RESET) Section ............................ 23 Changes to Ordering Guide .......................................................... 27 Rev. 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