Quad, 16-Bit nanoDAC+ with 4 ppm/C Reference, SPI Interface Enhanced Product AD5686R-EP FEATURES FUNCTIONAL BLOCK DIAGRAM V GND V DD REF High relative accuracy (INL): 4 LSB maximum at 16 bits Low drift 2.5 V reference: 4 ppm/C typical AD5686R-EP 2.5V REFERENCE Tiny package: 3 mm 3 mm, 16-lead LFCSP V LOGIC INPUT DAC STRING V A Total unadjusted error (TUE): 0.1% of FSR maximum OUT REGISTER REGISTER DAC A SCLK BUFFER Offset error: 1.5 mV maximum STRING INPUT DAC Gain error: 0.1% of FSR maximum V B OUT REGISTER REGISTER DAC B SYNC BUFFER High drive capability: 15 mA, 0.5 V from supply rails STRING INPUT DAC User selectable gain of 1 or 2 (GAIN pin) SDIN V C OUT DAC C REGISTER REGISTER BUFFER Reset to zero scale or midscale (RSTSEL pin) SDO INPUT DAC STRING 1.8 V logic compatibility V D OUT REGISTER REGISTER DAC D BUFFER 50 MHz SPI with readback or daisy chain POWER-ON GAIN POWER- Low glitch: 0.5 nV-sec RESET 1/2 DOWN LOGIC Low power: 3.3 mW at 3 V LDAC RESET RSTSEL GAIN 2.7 V to 5.5 V power supply Figure 1. ENHANCED PRODUCT FEATURES Supports defense and aerospace applications (AQEC) Temperature range: 55C to +125C Controlled manufacturing baseline 1 assembly/test site 1 fabrication site Enhanced product change notification Qualification data available on request APPLICATIONS Optical transceivers Base-station power amplifiers Process control (PLC input/output cards) Industrial automation Data acquisition systems reduces the current consumption of the device to 4 A at 3 V GENERAL DESCRIPTION while in power-down mode. The AD5686R-EP, a member of the nanoDAC+ family, is a low power, quad, 16-bit buffered voltage output digital-to-analog The AD5686R-EP employs a versatile serial peripheral interface converter (DAC). The device includes a 2.5 V, 4 ppm/C internal (SPI) that operates at clock rates up to 50 MHz, and contains a V pin that is intended for 1.8 V/3 V/5 V logic. reference (enabled by default) and a gain select pin giving a full- LOGIC scale output of 2.5 V (gain = 1) or 5 V (gain = 2). The device Additional application and technical information can be found operates from a single 2.7 V to 5.5 V supply, is guaranteed in the AD5686R/AD5685R/AD5684R data sheet. monotonic by design, and exhibits less than 0.1% FSR gain error PRODUCT HIGHLIGHTS and 1.5 mV offset error performance. The device is available in a 3 mm 3 mm LFCSP package. 1. High Relative Accuracy (INL). 4 LSB maximum. The AD5686R-EP also incorporates a power-on reset circuit and a 2. Low Drift 2.5 V On-Chip Reference. RSTSEL pin that ensures that the DAC outputs power up to zero 4 ppm/C typical temperature coefficient. scale or midscale and remains there until a valid write occurs. 13 ppm/C maximum temperature coefficient. The device contains a per-channel power-down feature that Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20152016 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. INTERFACE LOGIC 12975-001AD5686R-EP Enhanced Product TABLE OF CONTENTS Features .............................................................................................. 1 Timing Characteristics .................................................................6 Enhanced Product Features ............................................................ 1 Daisy-Chain and Readback Timing Characteristics ................7 Applications ....................................................................................... 1 Absolute Maximum Ratings ............................................................9 Functional Block Diagram .............................................................. 1 ESD Caution...................................................................................9 General Description ......................................................................... 1 Pin Configuration and Function Descriptions ........................... 10 Product Highlights ....................................................................... 1 Typical Performance Characteristics ........................................... 11 Revision History ........................................................................... 2 Outline Dimensions ....................................................................... 17 Specifications ..................................................................................... 3 Ordering Guide .......................................................................... 17 AC Characteristics ........................................................................ 5 REVISION HISTORY 11/2016Rev. 0 to Rev. A Changed 1.8 V VLOGIC 5.5 V to 1.62 V VLOGIC 5.5 V ................................................. Throughout Changes to Features Section............................................................ 1 Changes to V Parameter, Table 1 ...................................................... 4 LOGIC Changes to Output Noise Spectral Density (NSD) Parameter, Test Conditions/Comments Column, Table 2 .............................. 5 Changes to Table 3 ............................................................................ 6 Changes to Table 4 and Figure 4 ..................................................... 7 Changes to Figure 5 .......................................................................... 8 Deleted ESD Parameter, Table 5 and FICDM Parameter, Table 5 .... 9 Changes to Pin 9 Description Column, Table 6 and Pin 13 Description Column, Table 6 ........................................................ 10 Changes to Figure 9 ........................................................................ 11 Changes to Figure 15 to Figure 18 ................................................ 12 Changes to Figure 19 to Figure 23 ................................................ 13 Changes to Figure 25, Figure 26, and Figure 29 ......................... 14 Changes to Figure 31 and Figure 36 ............................................. 16 Changes to Figure 37 ...................................................................... 16 7/2015Revision 0: Initial Version Rev. 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