Dual, 16-/12-Bit nanoDAC+ with SPI Interface Data Sheet AD5689/AD5687 FEATURES FUNCTIONAL BLOCK DIAGRAM V V DD GND REF High relative accuracy (INL): 2 LSB maximum at 16 bits Tiny package: 3 mm 3 mm, 16-lead LFCSP AD5689/AD5687 V LOGIC TUE: 0.1% of FSR maximum SCLK Offset error: 1.5 mV maximum INPUT DAC Gain error: 0.1% of FSR maximum STRING V A OUT REGISTER REGISTER DAC A SYNC BUFFER High drive capability: 20 mA, 0.5 V from supply rails User-selectable gain of 1 or 2 (GAIN pin) INPUT DAC STRING SDIN V B OUT REGISTER REGISTER DAC B Reset to zero scale or midscale (RSTSEL pin) BUFFER 1.8 V logic compatibility SDO 50 MHz SPI with readback or daisy chain Low glitch: 0.5 nV-sec POWER-ON GAIN = POWER- RESET 1/2 DOWN LOGIC Low power: 3.3 mW at 3 V 2.7 V to 5.5 V power supply LDAC RESET RSTSEL GAIN 40C to +105C temperature range Figure 1. APPLICATIONS Optical transceivers Base station power amplifiers Process control (PLC I/O cards) Industrial automation Data acquisition systems GENERAL DESCRIPTION The AD5689/AD5687 members of the nanoDAC+ family are Table 1. Related Devices low power, dual, 16-/12-bit, buffered voltage output digital-to- Interface Reference 16-Bit 12-Bit analog converters (DACs). The devices include a gain select pin SPI Internal AD5689R AD5687R giving a full-scale output of 2.5 V (gain = 1) or 5 V (gain = 2). The External AD5689 AD5687 AD5689/AD5687 operate from a single 2.7 V to 5.5 V supply, are 2 I C Internal Not applicable AD5697R guaranteed monotonic by design, and exhibit less than 0.1% FSR gain error and 1.5 mV offset error performance. Both devices are available in a 3 mm 3 mm LFCSP and a TSSOP package. PRODUCT HIGHLIGHTS The AD5689/AD5687 also incorporate a power-on reset circuit 1. High Relative Accuracy (INL). and a RSTSEL pin that ensure that the DAC outputs power up AD5689 (16-bit): 2 LSB maximum to zero scale or midscale and remain there until a valid write AD5687 (12-bit): 1 LSB maximum takes place. Each part contains a per channel power-down feature 2. Excellent DC Performance. that reduces the current consumption of the device to 4 A at Total unadjusted error: 0.1% of FSR maximum 3 V while in power-down mode. Offset error: 1.5 mV maximum Gain error: 0.1% of FSR maximum The AD5689/AD5687 use a versatile serial peripheral interface 3. Two Package Options. that operates at clock rates up to 50 MHz. Both devices contain 3 mm 3 mm, 16-lead LFCSP a VLOGIC pin that is intended for 1.8 V/3 V/5 V logic. 16-lead TSSOP Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20132017 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com INTERFACE LOGIC 11255-001AD5689/AD5687 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Serial Interface ............................................................................ 18 Applications ....................................................................................... 1 Standalone Operation ................................................................ 19 Functional Block Diagram .............................................................. 1 Write and Update Commands .................................................. 19 General Description ......................................................................... 1 Daisy-Chain Operation ............................................................. 19 Product Highlights ........................................................................... 1 Readback Operation .................................................................. 20 Revision History ............................................................................... 2 Power-Down Operation ............................................................ 20 Specifications ..................................................................................... 3 LDAC Load DAC (Hardware Pin) ........................................... 21 AC Characteristics ........................................................................ 4 LDAC Mask Register ................................................................. 21 Timing Characteristics ................................................................ 5 Hardware Reset (RESET) .......................................................... 22 Daisy-Chain and Readback Timing Characteristics................ 6 Reset Select Pin (RSTSEL) ........................................................ 22 Absolute Maximum Ratings ............................................................ 8 Applications Information .............................................................. 23 ESD Caution .................................................................................. 8 Microprocessor Interfacing ....................................................... 23 Pin Configurations and Function Descriptions ........................... 9 AD5689/AD5687 to ADSP-BF531 Interface .......................... 23 Typical Performance Characteristics ........................................... 10 AD5689/AD5687 to SPORT Interface..................................... 23 Terminology .................................................................................... 15 Layout Guidelines....................................................................... 23 Theory of Operation ...................................................................... 17 Galvanically Isolated Interface ................................................. 23 Digital-to-Analog Converters (DACs) .................................... 17 Outline Dimensions ....................................................................... 24 Transfer Function ....................................................................... 17 Ordering Guide .......................................................................... 24 DAC Architecture ....................................................................... 17 REVISION HISTORY 7/2017Rev. A to Rev. B 1/2016Rev. 0 to Rev. A Changes to Features Section and Table 1 ...................................... 1 Change to Table 14 ......................................................................... 21 Changes to Table 2 ............................................................................ 3 Changes to Table 3 Summary .......................................................... 4 2/2013Revision 0: Initial Version Changes to Table 4 and Figure 2 ..................................................... 5 Changes to Table 5 and Figure 4 ..................................................... 6 Changes to Figure 5 .......................................................................... 7 Changes to Table 6 ............................................................................ 8 Change to V Pin Description and RESET Pin Description, LOGIC Table 7 ................................................................................................ 9 Changes to Figure 10 and Figure 13............................................. 10 Changes to Figure 14 and Figure 19............................................. 11 Changes to Figure 20 and Figure 25............................................. 12 Changes to Figure 32 ...................................................................... 14 Changes to Table 9 .......................................................................... 18 Changes to Readback Operation Section .................................... 20 Changes to Hardware Reset (RESET) Section ............................ 22 Rev. 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