Dual, 16-/12-Bit nanoDAC+ with 2 ppm/C Reference, SPI Interface Data Sheet AD5689R/AD5687R FEATURES FUNCTIONAL BLOCK DIAGRAM V V DD GND REF High relative accuracy (INL): 2 LSB maximum at 16 bits Low drift 2.5 V reference: 2 ppm/C typical AD5689R/AD5687R V LOGIC 2.5V REFERENCE Tiny package: 3 mm 3 mm, 16-lead LFCSP SCLK TUE: 0.1% of FSR maximum INPUT DAC STRING V A Offset error: 1.5 mV maximum OUT REGISTER REGISTER DAC A SYNC BUFFER Gain error: 0.1% of FSR maximum INPUT DAC STRING V B High drive capability: 20 mA, 0.5 V from supply rails SDIN OUT REGISTER REGISTER DAC B BUFFER User-selectable gain of 1 or 2 (GAIN pin) Reset to zero scale or midscale (RSTSEL pin) SDO 1.8 V logic compatibility POWER-ON GAIN = POWER- 50 MHz SPI with readback or daisy chain RESET 1/2 DOWN LOGIC Low glitch: 0.5 nV-sec LDAC RESET RSTSEL GAIN Low power: 3.3 mW at 3 V Figure 1. 2.7 V to 5.5 V power supply 40C to +105C temperature range AEC-Q100 qualified for automotive applications APPLICATIONS Optical transceivers Base station power amplifiers Process control (PLC I/O cards) Industrial automation Data acquisition systems GENERAL DESCRIPTION The AD5689R/AD5687R members of the nanoDAC+ Table 1. Dual nanoDAC+ Devices family are low power, dual, 16-/12-bit buffered voltage output Interface Reference 16-Bit 12-Bit digital-to-analog converters (DACs). The devices include SPI Internal AD5689R AD5687R a 2.5 V, 2 ppm/C internal reference (enabled by default) External AD5689 AD5687 and a gain select pin giving a full-scale output of 2.5 V 2 IC Internal AD5697R (gain = 1) or 5 V (gain = 2). The devices operate from a single 2.7 V to 5.5 V supply, are guaranteed monotonic by design, and exhibit less than 0.1% FSR gain error and PRODUCT HIGHLIGHTS 1.5 mV offset error performance. Both devices are 1. High Relative Accuracy (INL). available in a 3 mm 3 mm LFCSP and a TSSOP package. AD5689R (16-bit): 2 LSB maximum The AD5689R/AD5687R also incorporate a power-on reset AD5687R (12-bit): 1 LSB maximum circuit and a RSTSEL pin that ensure that the DAC outputs 2. Low Drift 2.5 V On-Chip Reference. power up to zero scale or midscale and remain there until 2 ppm/C typical temperature coefficient a valid write takes place. Each part contains a per channel 5 ppm/C maximum temperature coefficient power-down feature that reduces the current consumption 3. Two Package Options. of the device to 4 A at 3 V while in power-down mode. 3 mm 3 mm, 16-lead LFCSP The AD5689R/AD5687R use a versatile serial peripheral 16-lead TSSOP interface (SPI) that operates at clock rates up to 50 MHz. Both devices contain a VLOGIC pin that is intended for 1.8 V/3 V/5 V logic. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. 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INTERFACE LOGIC 11256-001AD5689R/AD5687R Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Daisy-Chain Operation ............................................................. 21 Applications ....................................................................................... 1 Readback Operation .................................................................. 22 Functional Block Diagram .............................................................. 1 Power-Down Operation ............................................................ 22 General Description ......................................................................... 1 LDAC Load DAC (Hardware Pin) ........................................... 23 Product Highlights ........................................................................... 1 LDAC Mask Register ................................................................. 23 Revision History ............................................................................... 2 Hardware Reset ( ) .......................................................... 24 RESET Specif icat ions ..................................................................................... 3 Reset Select Pin (RSTSEL) ........................................................ 24 AC Characteristics ........................................................................ 5 Internal Reference Setup ........................................................... 24 Timing Characteristics ................................................................ 6 Solder Heat Reflow ..................................................................... 24 Daisy-Chain and Readback Timing Characteristics ............... 7 Long-Term Temperature Drift ................................................. 24 Absolute Maximum Ratings ............................................................ 9 Thermal Hysteresis .................................................................... 25 ESD Caution .................................................................................. 9 Applications Information .............................................................. 26 Pin Configurations and Function Descriptions ......................... 10 Microprocessor Interfacing ....................................................... 26 Typical Performance Characteristics ........................................... 11 AD5689R/AD5687R to ADSP-BF531 Interface ...................... 26 Terminology .................................................................................... 17 AD5689R/AD5687R to SPORT Interface ................................ 26 Theory of Operation ...................................................................... 19 Layout Guidelines....................................................................... 26 Digital-to-Analog Converters ................................................... 19 Galvanically Isolated Interface ................................................. 26 Transfer Function ....................................................................... 19 Outline Dimensions ....................................................................... 27 DAC Architecture ....................................................................... 19 Ordering Guide .......................................................................... 28 Serial Interface ............................................................................ 20 Automotive Products ................................................................. 28 Standalone Operation ................................................................ 21 Write and Update Commands .................................................. 21 REVISION HISTORY 10/2019Rev. B to Rev. C Changes to Figure 12 ...................................................................... 11 Changes to Features Section............................................................ 1 Changes to Figure 19 ...................................................................... 12 Changes to AD5689R, Relative Accuracy Parameter, Table 2 ......... 3 Changes to Figure 20 to Figure 23 and Figure 25 ...................... 13 Updated Outline Dimensions ......................................................... 27 Changes to Figure 26, Figure 27, Figure 29, and Figure 30....... 14 Added Automotive Products Section .......................................... 28 Changes to Figure 33, Figure 36, and Figure 37 ......................... 15 Changes to Ordering Guide .......................................................... 28 Change to Table 9 ........................................................................... 20 Change to Readback Operation Section ..................................... 22 3/2017Rev. A to Rev. B Change to Table 14 ......................................................................... 23 Changes to Features and Table 1 .................................................... 1 Changes to Hardware Reset Section and Reset Select Pin Changed 1.8 V V 5.5 V to 1.62 V V 5.5 V ......... 3 (RSTSEL) Section ........................................................................... 24 LOGIC LOGIC Change to VLOGIC Parameter, Table 2 .............................................. 4 Added Long-Term Temperature Drift Section and Figure 49 Changed 1.8 V VLOGIC 5.5 V to 1.8 V 10% VLOGIC 5 V + Renumbered Sequentially ............................................................. 24 10% ..................................................................................................... 5 Changed 1.8 V VLOGIC 5.5 V to 1.62 V VLOGIC 5.5 V ......... 6 5/2014Rev. 0 to Rev. A Changes to Table 4 and Figure 2 ..................................................... 6 Deleted Long-Term Stability/Drift Parameter, Table 1 ................ 4 Changed 1.8 V V 5.5 V to 1.62 V V 5.5 V ......... 7 Deleted Figure 11 Renumbered Sequentially ............................ 11 LOGIC LOGIC Changes to Table 5 and Figure 4 ..................................................... 7 Deleted Long-Term Temperature Drift Section ......................... 24 Changes to Figure 5 .......................................................................... 8 Changes to Table 6 ............................................................................ 9 2/2013Revision 0: Initial Version Changes to Table 7 .......................................................................... 10 Rev. C Page 2 of 28