12-Bit Ultrahigh Speed a Monolithic D/A Converter AD568 FUNCTIONAL BLOCK DIAGRAM FEATURES Ultrahigh Speed: Current Settling to 1 LSB in 35 ns High Stability Buried Zener Reference on Chip Monotonicity Guaranteed Over Temperature 10.24 mA Full-Scale Output Suitable for Video Applications Integral and Differential Linearity Guaranteed Over Temperature 0.3 Skinny DIP Packaging Variable Threshold Allows TTL and CMOS Interface MIL-STD-883 Compliant Versions Available PRODUCT DESCRIPTION PRODUCT HIGHLIGHTS The AD568 is an ultrahigh-speed, 12-bit digital-to-analog con- 1. The ultrafast settling time of the AD568 allows leading edge verter (DAC) settling to 0.025% in 35 ns. The monolithic de- performance in waveform generation, graphics display and vice is fabricated using Analog Devices Complementary Bipolar high speed A/D conversion applications. (CB) Process. This is a proprietary process featuring high-speed 2. Pin strapping provides a variety of voltage and current output NPN and PNP devices on the same chip without the use of di- ranges for application versatility. Tight control of the abso- electric isolation or multichip hybrid techniques. The high speed lute output current reduces trim requirements in externally- of the AD568 is maintained by keeping impedance levels low scaled applications. enough to minimize the effects of parasitic circuit capacitances. 3. Matched on-chip resistors can be used for precision scaling in The DAC consists of 16 current sources configured to deliver a high speed A/D conversion circuits. 10.24 mA full-scale current. Multiple matched current sources and thin-film ladder techniques are combined to produce bit 4. The digital inputs are compatible with TTL and +5 V weighting. The DACs output is a 10.24 mA full scale (FS) for CMOS logic families. current output applications or a 1.024 V FS unbuffered voltage 5. Skinny DIP (0.3 ) packaging minimizes board space require- output. Additionally, a 10.24 V FS buffered output may be gen- ments and eases layout considerations. erated using an onboard 1 k span resistor with an external op 6. The AD568 is available in versions compliant with MIL- amp. Bipolar ranges are accomplished by pin strapping. STD-883. Refer to the Analog Devices Military Products Laser wafer trimming insures full 12-bit linearity. All grades of Databook or current AD568/883B data sheet for detailed the AD568 are guaranteed monotonic over their full operating specifications. temperature range. Furthermore, the output resistance of the DAC is trimmed to 100 1.0%. The gain temperature coeffi- cient of the voltage output is 30 ppm/C max (K). The AD568 is available in three performance grades. The AD568JQ and KQ are available in 24-pin cerdip (0.3 ) packages and are specified for operation from 0C to +70C. The AD568SQ features operation from 55C to +125C and is also packaged in the hermetic 0.3 cerdip. REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 617/329-4700 Fax: 617/326-8703( = +258C, V , V = 615 V unless otherwise noted) AD568SPECIFICATIONS CC EE Model AD568J AD568K AD568S Min Typ Max Min Typ Max Min Typ Max Units RESOLUTION 12 12 12 Bits 1 ACCURACY Linearity 1/2 +1/2 1/4 +1/4 1/2 +1/2 LSB T to T 3/4 +3/4 1/2 +1/2 3/4 +3/4 LSB MIN MAX Differential Nonlinearity 1 +1 1/2 +1/2 1 +1 LSB T to T 1 +1 1 + 1 1 1 LSB MIN MAX Monotonicity GUARANTEED OVER RATED SPECIFICATION TEMPERATURE RANGE Unipolar Offset 0.2 +0.2 * * * * % of FSR Bipolar Offset 1.0 +1.0 * * * * % of FSR Bipolar Zero 0.2 +0.2 * * * * % of FSR Gain Error 1.0 +1.0 * * * * % of FSR 2 TEMPERATURE COEFFICIENTS Unipolar Offset 5 +5 3 +3 5 +5 ppm of FSR/C Bipolar Offset 30 +30 20 +20 30 +30 ppm of FSR/C Bipolar Zero 15 +15 ppm of FSR/C Gain Drift 50 +50 30 +30 50 +50 ppm of FSR/C Gain Drift (I ) 150 +150 * * * * ppm of FSR/C OUT DATA INPUTS Logic Levels (T to T ) MIN MAX V 2.0 7.0** ** V IH V 0.0 0.8** ** V IL Logic Currents (T to T ) MIN MAX I 10 0 +10 ** * * ** A IH I 0.5 60 100 * * * * 100 200 A IL V Pin Voltage 1.4 * * V TH CODING BINARY, OFFSET BINARY CURRENT OUTPUT RANGES 0 to 10.24, 5.12 mA VOLTAGE OUTPUT RANGES 0 to 1.024, 0.512 V COMPLIANCE VOLTAGE 2 +1.2 * * * * V OUTPUT RESISTANCE Exclusive of R 160 200 240 * * L Inclusive of R 99 100 101 * * L SETTLING TIME Current to 0.025% 35 * * ns to 0.025% of FSR 0.1% 23 * * ns to 0.1% of FSR Voltage 3 50 Load , 0.512 V p-p, to 0.025% 37 * * ns to 0.025% of FSR to 0.1% 25 * * ns to 0.1% of FSR to 1% 18 * * ns to 1% of FSR 3 75 Load , 0.768 V p-p, to 0.025% 40 * * ns to 0.025% of FSR to 0.1% 25 * * ns to 0.1% of FSR to 1% 20 * * ns to 1% of FSR 3 100 (Internal R ) , 1.024 V p-p, L to 0.025% 50 * * ns to 0.025% of FSR to 0.1% 38 * * ns to 0.1% of FSR to 1% 24 * * ns to 1% of FSR 4 Glitch Impulse 350 * * pV-sec Peak Amplitude 15 * * % of FSR 5 FULL-SCALE TRANSlTlON 10% to 90% Rise Time 11 * * ns 90% to 10% Fall Time 11 * * ns POWER REQUIREMENTS +13.5 V to +16.5 V 27 32 ** * * mA 13.5 V to 16.5 V 7 8 ** * * mA Power Dissipation 525 625 * * * * mW PSRR 0.05 * * % of FSR/V TEMPERATURE RANGE 2 Rated Specification 0 +70 0 +70 55 +125 C Storage 65 +150 * * * * C NOTES *Same as AD568J. 1 Measured in I mode. OUT 2 Measured in V mode, unless otherwise specified. See text for further information. OUT 3 Total Resistance. Refer to Figure 3, 4 At the major carry, driven by HCMOS logic. See text for further explanation. 5 Measured in V mode. OUT Specifications shown in boldface are tested on all production units at final electrical test. Specifications subject to change without notice. 2 REV. A