Quad 16-/14-/12-Bit nanoDAC+ 2 with 2 ppm/C Reference, I C Interface Data Sheet AD5696R/AD5695R/AD5694R FEATURES FUNCTIONAL BLOCK DIAGRAM High relative accuracy (INL): 2 LSB maximum at 16 bits V GND V DD REF Low drift 2.5 V reference: 2 ppm/C typical Tiny package: 3 mm 3 mm, 16-lead LFCSP AD5696R/AD5695R/AD5694R 2.5V REFERENCE Total unadjusted error (TUE): 0.1% of FSR maximum V LOGIC Offset error: 1.5 mV maximum INPUT DAC STRING V A OUT DAC A REGISTER REGISTER Gain error: 0.1% of FSR maximum SCL BUFFER High drive capability: 20 mA, 0.5 V from supply rails INPUT DAC STRING V B OUT REGISTER REGISTER DAC B SDA User selectable gain of 1 or 2 (GAIN pin) BUFFER Reset to zero scale or midscale (RSTSEL pin) INPUT DAC STRING A1 V C OUT 1.8 V logic compatibility REGISTER REGISTER DAC C BUFFER Low glitch: 0.5 nV-sec A0 2 STRING INPUT DAC 400 kHz I C-compatible serial interface V D OUT REGISTER REGISTER DAC D BUFFER Low power: 3.3 mW at 3 V POWER-ON GAIN = POWER- 2.7 V to 5.5 V power supply RESET 1/2 DOWN LOGIC 40C to +105C temperature range LDAC RESET RSTSEL GAIN APPLICATIONS Figure 1. Optical transceivers Base-station power amplifiers Process control (PLC I/O cards) Industrial automation Data acquisition systems GENERAL DESCRIPTION The AD5696R/AD5695R/AD5694R family are low power, quad, Table 1. Quad nanoDAC+ Devices 16-/14-/12-bit buffered voltage output DACs. The devices include Interface Reference 16-Bit 14-Bit 12-Bit a 2.5 V, 2 ppm/C internal reference (enabled by default) and a SPI Internal AD5686R AD5685R AD5684R gain select pin giving a full-scale output of 2.5 V (gain = 1) or External AD5686 AD5684 5 V (gain = 2). All devices operate from a single 2.7 V to 5.5 V 2 I C Internal AD5696R AD5695R AD5694R supply, are guaranteed monotonic by design, and exhibit less External AD5696 AD5694 than 0.1% FSR gain error and 1.5 mV offset error performance. The devices are available in a 3 mm 3 mm LFCSP and a TSSOP package. PRODUCT HIGHLIGHTS The AD5696R/AD5695R/AD5694R also incorporate a power- 1. High Relative Accuracy (INL). on reset circuit and a RSTSEL pin that ensures that the DAC AD5696R (16-bit): 2 LSB maximum. outputs power up to zero scale or midscale and remain there AD5695R (14-bit): 1 LSB maximum. until a valid write takes place. Each part contains a per-channel AD5694R (12-bit): 1 LSB maximum. power-down feature that reduces the current consumption of 2. Low Drift 2.5 V On-Chip Reference. the device to 4 A at 3 V while in power-down mode. 2 ppm/C typical temperature coefficient. 5 ppm/C maximum temperature coefficient. The AD5696R/AD5695R/AD5694R use a versatile 2-wire serial 3. Two Package Options. interface that operates at clock rates up to 400 kHz, and includes 3 mm 3 mm, 16-lead LFCSP. a VLOGIC pin intended for 1.8 V/3 V/5 V logic. 16-lead TSSOP. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20122017 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com INTERFACE LOGIC 10486-001AD5696R/AD5695R/AD5694R Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Serial Operation ......................................................................... 21 Applications ....................................................................................... 1 Write Operation.......................................................................... 21 Functional Block Diagram .............................................................. 1 Read Operation........................................................................... 22 General Description ......................................................................... 1 Multiple DAC Readback Sequence .......................................... 22 Product Highlights ........................................................................... 1 Power-Down Operation ............................................................ 23 Revision History ............................................................................... 2 LDAC Load DAC (Hardware Pin) ........................................... 24 Specif icat ions ..................................................................................... 3 LDAC Mask Register ................................................................. 24 AC Characteristics ........................................................................ 5 Hardware Reset ( ) .......................................................... 25 RESET Timing Characteristics ................................................................ 6 Reset Select Pin (RSTSEL) ........................................................ 25 Absolute Maximum Ratings ............................................................ 7 Internal Reference Setup ........................................................... 25 ESD Caution .................................................................................. 7 Solder Heat Reflow ..................................................................... 25 Pin Configuration and Function Descriptions ............................. 8 Long-Term Temperature Drift ................................................. 25 Typical Performance Characteristics ............................................. 9 Thermal Hysteresis .................................................................... 26 Terminology .................................................................................... 16 Applications Information .............................................................. 27 Theory of Operation ...................................................................... 18 Microprocessor Interfacing ....................................................... 27 Digital-to-Analog Converter .................................................... 18 AD5696R/AD5695R/AD5694R to ADSP-BF531 Interface .... 27 Transfer Function ....................................................................... 18 Layout Guidelines....................................................................... 27 DAC Architecture ....................................................................... 18 Galvanically Isolated Interface ................................................. 27 Serial Interface ............................................................................ 19 Outline Dimensions ....................................................................... 28 Write and Update Commands .................................................. 20 Ordering Guide .......................................................................... 29 REVISION HISTORY 4/2017Rev. C to Rev. D 5/2014Rev. B to Rev. C Changes to Features Section............................................................ 1 Deleted Long-Term Stability Drift Parameter, Table 1 ................. 4 Changes to Specifications Section .................................................. 3 Deleted Figure 8 Renumbered Sequentially ................................. 9 Changes to VLOGIC Parameter, Table 1 ............................................ 4 Changes to Read Operation Section and Figure 51 ................... 22 Changes to AC Characteristics Section and Output Noise Deleted Long-Term Temperature Drift Section ......................... 25 Spectral Density Parameter, Table 3 ............................................... 5 Changes to Timing Characteristics Section .................................. 6 6/2013Rev. A to Rev. B Changes to Table 5 ............................................................................ 7 Changes to Pin GAIN and Pin RSTSEL Descriptions Table 6 ... 8 Changes to V Pin Description and RESET Pin Description, LOGIC 11/2012Rev. 0 to Rev. A Table 6 ................................................................................................ 8 Changes to Table 1 ............................................................................. 1 Changes to Figure 18 to Figure 22 ................................................ 11 Changes to Table 4 ............................................................................. 6 Changes to Figure 23 to Figure 26 and Figure 28 ...................... 12 Changes to Figure 10......................................................................... 9 Changes to Figure 29, Figure 32, and Figure 34 ......................... 13 Changes to Figure 33...................................................................... 13 Changes to Figure 39 and Figure 40............................................. 14 Changes to Serial Interface Section .............................................. 19 Changes to Figure 50 ...................................................................... 21 Changes to Figure 52...................................................................... 22 Changes to Figure 51 ...................................................................... 22 Changes to Hardware Reset (RESET) Section ............................ 25 4/2012Revision 0: Initial Version Added Long-Term Temperature Drift Section and Figure 55 Renumbered Sequentially ................................................................... 25 Changes to Ordering Guide ................................................................ 29 Rev. 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