Quad, 16-/12-Bit nanoDAC+ 2 with I C Interface Data Sheet AD5696/AD5694 FEATURES FUNCTIONAL BLOCK DIAGRAM High relative accuracy (INL): 2 LSB maximum at 16 bits V GND V DD REF Tiny package: 3 mm 3 mm, 16-lead LFCSP AD5696/AD5694 Total unadjusted error (TUE): 0.1% of FSR maximum Offset error: 1.5 mV maximum V LOGIC INPUT DAC STRING V A OUT Gain error: 0.1% of FSR maximum DAC A REGISTER REGISTER SCL BUFFER High drive capability: 20 mA, 0.5 V from supply rails INPUT DAC STRING User-selectable gain of 1 or 2 (GAIN pin) V B OUT REGISTER REGISTER DAC B SDA Reset to zero scale or midscale (RSTSEL pin) BUFFER 1.8 V logic compatibility STRING INPUT DAC A1 V C OUT REGISTER REGISTER DAC C 2 400 kHz I C-compatible serial interface BUFFER 2 4 I C addresses available A0 INPUT DAC STRING V D OUT REGISTER REGISTER DAC D Low glitch: 0.5 nV-sec BUFFER Low power: 1.8 mW at 3 V POWER-ON GAIN = POWER- 2.7 V to 5.5 V power supply RESET 1/2 DOWN LOGIC 40C to +105C temperature range LDAC RESET RSTSEL GAIN APPLICATIONS Figure 1. Digital gain and offset adjustment Programmable attenuators Process control (PLC I/O cards) Industrial automation Data acquisition systems GENERAL DESCRIPTION The AD5696 and AD5694, members of the nanoDAC+ family, Table 1. Quad nanoDAC+ Devices are low power, quad, 16-/12-bit buffered voltage output DACs. Interface Reference 16-Bit 14-Bit 12-Bit The devices include a gain select pin giving a full-scale output SPI Internal AD5686R AD5685R AD5684R of 2.5 V (gain = 1) or 5 V (gain = 2). The devices operate from External AD5686 AD5684 2 a single 2.7 V to 5.5 V supply, are guaranteed monotonic by IC Internal AD5696R AD5695R AD5694R design, and exhibit less than 0.1% FSR gain error and 1.5 mV External AD5696 AD5694 offset error performance. The devices are available in a 3 mm 3 mm LFCSP package and in a TSSOP package. PRODUCT HIGHLIGHTS 1. High Relative Accuracy (INL). The AD5696/AD5694 incorporate a power-on reset circuit and a AD5696 (16-bit): 2 LSB maximum RSTSEL pin the RSTSEL pin ensures that the DAC outputs power up to zero scale or midscale and remain at that level until a AD5694 (12-bit): 1 LSB maximum valid write takes place. The parts contain a per-channel power- 2. Excellent DC Performance. Total unadjusted error: 0.1% of FSR maximum down feature that reduces the current consumption of the Offset error: 1.5 mV maximum device in power-down mode to 4 A at 3 V. Gain error: 0.1% of FSR maximum The AD5696/AD5694 use a versatile 2-wire serial interface that 3. Two Package Options. operates at clock rates up to 400 kHz and include a V pin LOGIC 3 mm 3 mm, 16-lead LFCSP intended for 1.8 V/3 V/5 V logic. 16-lead TSSOP Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. Tel: 781.329.4700 20122020 Analog Devices, Inc. All rights reserved. No license is granted by implication or otherwise under any patent or patent rights of Analog Technical Support www.analog.com Devices. Trademarks and registered trademarks are the property of their respective owners. INTERFACE LOGIC 10799-001AD5696/AD5694 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Write and Update Commands ................................................. 18 2 Applications ...................................................................................... 1 I C Slave Address ....................................................................... 18 Functional Block Diagram .............................................................. 1 Serial Operation.......................................................................... 18 General Description ......................................................................... 1 Write Operation ......................................................................... 18 Product Highlights ........................................................................... 1 Read Operation .......................................................................... 19 Revision History ............................................................................... 2 Multiple DAC Readback Sequence .......................................... 19 Specifications .................................................................................... 3 Power-Down Operation ............................................................ 20 AC Characteristics ....................................................................... 5 Load DAC (Hardware LDAC Pin) .......................................... 20 Timing Characteristics ................................................................ 6 LDAC Mask Register ................................................................. 21 Absolute Maximum Ratings ........................................................... 7 Hardware Reset Pin (RESET) ................................................... 21 Thermal Resistance ...................................................................... 7 Reset Select Pin (RSTSEL) ........................................................ 21 ESD Caution.................................................................................. 7 Applications Information ............................................................. 22 Pin Configurations and Function Descriptions ........................... 8 Microprocessor Interfacing ...................................................... 22 Typical Performance Characteristics ............................................. 9 AD5696/AD5694 to ADSP-BF531 Interface .......................... 22 Terminology .................................................................................... 14 Layout Guidelines ...................................................................... 22 Theory of Operation ...................................................................... 16 Galvanically Isolated Interface ................................................. 22 Digital-to-Analog Converter .................................................... 16 Outline Dimensions ....................................................................... 23 Transfer Function ...................................................................... 16 Ordering Guide .......................................................................... 24 DAC Architecture ...................................................................... 16 Serial Interface ............................................................................ 17 REVISION HISTORY 8/2020Rev. B to Rev. C RESET Changes to VLOGIC Pin Description and Pin Description, Changes to Figure 2 .......................................................................... 6 Table 7 ................................................................................................. 8 Updated Outline Dimensions ....................................................... 23 Changes to Figure 9 .......................................................................... 9 Changes to Ordering Guide .......................................................... 24 Changes to Figure 11 to Figure 16 ............................................... 10 Changes to Figure 17, Figure 19, and Figure 22 ........................ 11 11/2016Rev. A to Rev. B Changes to Figure 24 ..................................................................... 12 Changes to Features Section ........................................................... 1 Changes to Figure 29 ..................................................................... 13 Changes to Specifications Section .................................................. 3 Changes to Figure 38 ..................................................................... 19 Changes to VLOGIC Parameter, Table 1 ........................................... 4 RESET Changes to Hardware Reset Pin ( ) Section .................... 21 Changes to AC Characteristics Section ......................................... 5 Changes to Timing Characteristics Section .................................. 6 6/2013Rev. 0 to Rev. A Changes to Table 5 ........................................................................... 7 Changes to Pin GAIN and Pin RSTSEL Descriptions Table 7........ 8 7/2012Revision 0: Initial Version Rev. C Page 2 of 24