Dual, 12-Bit nanoDAC+ 2 with 2 ppm/C Reference, I C Interface Data Sheet AD5697R FEATURES FUNCTIONAL BLOCK DIAGRAM V V DD GND REF Low drift 2.5 V reference: 2 ppm/C typical Tiny package: 3 mm 3 mm, 16-lead LFCSP AD5697R 2.5V V Total unadjusted error (TUE): 0.1% of full-scale range (FSR) REFERENCE LOGIC SCL maximum Offset error: 1.5 mV maximum INPUT DAC STRING V A OUT REGISTER REGISTER SDA DAC A Gain error: 0.1% of FSR maximum BUFFER High drive capability: 20 mA, 0.5 V from supply rails A1 INPUT DAC STRING V B OUT REGISTER REGISTER DAC B User selectable gain of 1 or 2 (GAIN pin) BUFFER A0 Reset to zero scale or midscale (RSTSEL pin) 1.8 V logic compatibility Low glitch: 0.5 nV-sec POWER-ON GAIN = POWER- RESET 1/2 DOWN 2 400 kHz I C-compatible serial interface LOGIC Low power: 3.3 mW at 3 V LDAC RESET RSTSEL GAIN 2.7 V to 5.5 V power supply Figure 1. 40C to +105C temperature range APPLICATIONS Base station power amplifiers Process controls (programmable logic controller PLC I/O cards) Industrial automation Data acquisition systems GENERAL DESCRIPTION The AD5697R, a member of the nanoDAC+ family, is a low power, Table 1. Dual nanoDAC+ Devices dual, 12-bit buffered voltage output digital-to-analog converter Interface Reference 16-Bit 12-Bit (DAC). The device includes a 2.5 V, 2 ppm/C internal reference SPI Internal AD5689R AD5687R (enabled by default) and a gain select pin giving a full-scale output External AD5689 AD5687 of 2.5 V (gain = 1) or 5 V (gain = 2). The AD5697R operates from 2 I C Internal AD5697R a single 2.7 V to 5.5 V supply, is guaranteed monotonic by design, and exhibits less than 0.1% FSR gain error and 1.5 mV offset PRODUCT HIGHLIGHTS error performance. The device is available in a 3 mm 3 mm 1. Precision DC Performance. LFCSP and a TSSOP package. TUE: 0.1% of FSR maximum The AD5697R also incorporates a power-on reset circuit and a Offset error: 1.5 mV maximum RSTSEL pin that ensure that the DAC outputs power up to zero Gain error: 0.1% of FSR maximum scale or midscale and remain there until a valid write takes 2. Low Drift 2.5 V On-Chip Reference. place. It contains a per channel power-down feature that reduces 2 ppm/C typical temperature coefficient the current consumption of the device to 4 A at 3 V while in 5 ppm/C maximum temperature coefficient power-down mode. 3. Two Package Options. The AD5697R uses a versatile 2-wire serial interface that operates 3 mm 3 mm, 16-lead LFCSP at clock rates up to 400 kHz and includes a V pin intended LOGIC 16-lead TSSOP for 1.8 V/3 V/5 V logic. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20132016 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. 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Technical Support www.analog.com INTERFACE LOGIC 11253-001AD5697R Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Serial Operation ......................................................................... 19 Applications ....................................................................................... 1 Write Operation.......................................................................... 19 Functional Block Diagram .............................................................. 1 Read Operation........................................................................... 20 General Description ......................................................................... 1 Multiple DAC Readback Sequence .......................................... 20 Product Highlights ........................................................................... 1 Power-Down Operation ............................................................ 21 Revision History ............................................................................... 2 LDAC Load DAC (Hardware Pin) ........................................... 22 Specifications ..................................................................................... 3 LDAC Mask Register ................................................................. 22 AC Characteristics ........................................................................ 5 Hardware Reset ( ) .......................................................... 23 RESET Timing Characteristics ................................................................ 6 Reset Select Pin (RSTSEL) ........................................................ 23 Absolute Maximum Ratings ............................................................ 7 Internal Reference Setup ........................................................... 23 ESD Caution .................................................................................. 7 Solder Heat Reflow ..................................................................... 23 Pin Configurations and Function Descriptions ........................... 8 Long-Term Temperature Drift ................................................. 23 Typical Performance Characteristics ............................................. 9 Thermal Hysteresis .................................................................... 24 Terminology .................................................................................... 15 Applications Information .............................................................. 25 Theory of Operation ...................................................................... 17 Microprocessor Interfacing ....................................................... 25 Digital-to-Analog Converter .................................................... 17 AD5697R-to-ADSP-BF531 Interface ...................................... 25 Transfer Function ....................................................................... 17 Layout Guidelines....................................................................... 25 DAC Architecture ....................................................................... 17 Galvanically Isolated Interface ................................................. 25 Serial Interface ............................................................................ 18 Outline Dimensions ....................................................................... 26 Write and Update Commands .................................................. 18 Ordering Guide .......................................................................... 26 REVISION HISTORY 11/2016Rev. A to Rev. B Changes to Figure 35...................................................................... 14 Changes to Features Section and Table 1 ...................................... 1 Changes to Figure 44...................................................................... 20 Changes to Specifications Section .................................................. 3 Changes to Hardware Reset (RESET) Section ............................ 23 Changes to VLOGIC Parameter, Table 1 ............................................ 4 Added Long-Term Temperature Drift Section and Figure 48 Changes to AC Characteristics Section and Output Noise Renumbered Sequentially ............................................................. 23 Spectral Density Parameter, Table 3 ............................................... 5 Changes to Ordering Guide .......................................................... 26 Changes to Timing Characteristics Section .................................. 6 Changes to Table 5 ............................................................................ 7 1/2014Rev. 0 to Rev. A Changes to V Pin Description and RESET Pin Description, Removed Long-Term Stability/Drift Parameter ............................ 3 LOGIC Table 6 ................................................................................................ 8 Removed Figure 7 Renumbered Sequentially .............................. 9 Changes to Figure 7 and Figure 8 ................................................... 9 Removed Long-Term Temperature Drift Section and Figure 49 Changes to Figure 13 to Figure 16 ................................................ 10 Renumbered Sequentially ............................................................. 23 Changes to Figure 17 to Figure 21 ................................................ 11 Changes to Figure 23, Figure 24, and Figure 27 ......................... 12 2/2013Revision 0: Initial Version Changes to Figure 29 and Figure 34............................................. 13 Rev. B Page 2 of 27