16-Bit Monotonic a Voltage Output D/A Converter AD569 FUNCTIONAL BLOCK DIAGRAM FEATURES Guaranteed 16-Bit Monotonicity Monolithic BiMOS II Construction 60.01% Typical Nonlinearity 8- and 16-Bit Bus Compatibility 3 ms Settling to 16 Bits Low Drift Low Power Low Noise APPLICATIONS Robotics Closed-Loop Positioning High-Resolution ADCs Microprocessor-Based Process Control MIL-STD-883 Compliant Versions Available PRODUCT DESCRIPTION The AD569 is a monolithic 16-bit digital-to-analog converter (DAC) manufactured in Analog Devices BiMOS II process. BiMOS II allows the fabrication of low power CMOS logic functions on the same chip as high precision bipolar linear cir- cuitry. The AD569 chip includes two resistor strings, selector switches decoding logic, buffer amplifiers, and double-buffered input latches. PRODUCT HIGHLIGHTS 1. Monotonicity to 16 bits is insured by the AD569s voltage- The AD569s voltage-segmented architecture insures 16-bit segmented architecture. monotonicity over time and temperature. Integral nonlinearity is maintained at 0.01%, while differential nonlinearity is 2. The output range is ratiometric to an external reference or ac 0.0004%. The on-chip, high-speed buffer amplifiers provide a signal. Gain error and gain drift of the AD569 are negligible. voltage output settling time of 3 s to within 0.001% for a 3. The AD569s versatile data input structure allows loading full-scale step. from 8- and 16-bit buses. The reference input voltage which determines the output range 4. The on-chip output buffer amplifier can supply 5 V into a can be either unipolar or bipolar. Nominal reference range is 1 k load, and can drive capacitive loads of up to 1000 pF. 5 V and separate reference force and sense connections are 5. Kelvin connections to the reference inputs preserve the gain provided for high accuracy applications. The AD569 can oper- and offset accuracy of the transfer function in the presence of ate with an ac reference in multiplying applications. wiring resistances and ground currents. Data may be loaded into the AD569s input latches from 8- and 6. The AD569 is available in versions compliant with MIL-STD- 16-bit buses. The double-buffered structure simplifies 8-bit bus 883. Refer to the Analog Devices Military Products Data- interfacing and allows multiple DACs to be loaded asynchro- book or current AD569/883B data sheet for detailed nously and updated simultaneously. Four TTL/LSTTL/5 V specifications. CMOS-compatible signals control the latches: CS, LBE, HBE, and LDAC The AD569 is available in five grades: J and K versions are specified from 0C to +70C and are packaged in a 28-pin plas- tic DIP and 28-pin PLCC package AD and BD versions are specified from 25C to +85C and are packaged in a 28-pin ceramic DIP. The SD version, also in a 28-pin ceramic DIP, is specified from 55C to +125C. REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 617/329-4700 Fax: 617/326-8703(T = +258C, +V = +12 V, V = 12 V, +V = +5 V, V = 5 V, unless A S S REF REF AD569SPECIFICATIONS otherwise noted.) Model AD569JN/JP/AD AD569KN/KP/BD AD569SD Parameter Min Typ Max Min Typ Max Min Typ Max Units RESOLUTION 16 16 16 Bits LOGIC INPUTS V (Logic l) 2.0 5.5 2.0 5.5 2.0 5.5 Volts IH V (Logic 0) 0 0.8 0 0.8 0 0.8 Volts IL I (V = 5.5 V) 10 10 10 A IH IH I (V = 0 V) 10 10 10 A IL IL TRANSFER FUNCTION CHARACTERISTICS 1 Integral Nonlinearity 0.02 60.04 0.01 60.024 60.04 % FSR T to T 0.02 60.04 0.020 60.024 60.04 % FSR MIN MAX Differential Nonlinearity 1/2 61 1/4 61/2 61 LSB T to T 1/2 61 1/2 61 61 LSB MIN MAX 2 Unipolar Offset 6500 6350 6500 V T to T 6750 6450 6750 V MIN MAX 2 Bipolar Offset 6500 6350 6500 V T to T 6750 6450 6750 V MIN MAX 2 Full Scale Error 6350 6350 6350 V T to T 6750 6750 6750 V MIN MAX 2 Bipolar Zero 60.04 60.024 60.04 % FSR T to T 60.04 60.024 60.04 % FSR MIN MAX REFERENCE INPUT 3 +V Range 5 +5 5 +5 5 +5 Volts REF V Range 5 +5 5 +5 5 +5 Volts REF 4 Resistance 15 20 25 15 20 25 15 20 25 k OUTPUT CHARACTERISTICS Voltage 5 +5 5 +5 5 +5 Volts Capacitive Load 1000 1000 1000 pF Resistive Load 1 1 1 k Short Circuit Current 10 10 10 mA POWER SUPPLIES Voltage +V +10.8 +12 +13.2 +10.8 +12 +13.2 +10.8 +12 +13.2 Volts S V 10.8 12 13.2 10.8 12 13.2 10.8 12 13.2 Volts S Current +I +9 +13 +9 +13 +9 +13 mA S I 9 13 9 13 9 13 mA S 5 Power Supply Sensitivity +10.8 V +V +13.2 V 0.5 62 0.5 62 0.5 62 ppm/% S 10.8 V V 13.2 V 1 63 1 63 1 63 ppm/% S TEMPERATURE RANGE Specified JN, KN, JP, KP 0 +70 0 +70 C AD, BD 25 +85 25 +85 C SD 55 +125 C Storage JN, KN, JP, KP 65 +150 65 +150 C AD, BD, SD 65 +150 65 +150 65 +150 C NOTES 1 FSR stands for Full-Scale Range, and is 10 V for a 5 V to +5 V span. 2 Refer to Definitions section. 3 For operation with supplies other than 12 V, refer to the Power Supply and Reference Voltage Range Section. 4 Measured between +V Force and V Force. REF REF 5 Sensitivity of Full-Scale Error due to changes in +V and sensitivity of Offset to changes in V . S S Specifications subject to change without notice. Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min and max specifications are guaranteed, although only those shown in boldface are tested on all production units. 2 REV. A