Multiple Range, 16-/12-Bit, Bipolar/Unipolar Voltage Output DACs with 2 ppm/C Reference Data Sheet AD5761R/AD5721R FEATURES GENERAL DESCRIPTION 8 software-programmable output ranges: 0 V to +5 V, 0 V to The AD5761R/AD5721R are single channel, 16-/12-bit serial +10 V, 0 V to +16 V, 0 V to +20 V, 3 V, 5 V, 10 V, and 2.5 V input, voltage output, digital-to-analog converters (DACs). to +7.5 V 5% overrange They operate from single supply voltages from +4.75 V to Low drift 2.5 V reference: 2 ppm/C typical +30 V or dual supply voltages from 16.5 V to 0 V VSS and Total unadjusted error (TUE): 0.1% FSR maximum +4.75 V to +16.5 V VDD. The integrated output amplifier, 16-bit resolution: 2 LSB maximum INL reference buffer, and reference provide a very easy to use, Guaranteed monotonicity: 1 LSB maximum universal solution. Single channel, 16-/12-bit DACs The devices offer guaranteed monotonicity, integral nonlinearity Settling time: 7.5 s typical (INL) of 2 LSB maximum, 35 nV/Hz noise, and 7.5 s settling Integrated reference buffers time on selected ranges. Low noise: 35 nV/Hz The AD5761R/AD5721R use a serial interface that operates at Low glitch: 1 nV-sec (0 V to 5 V range) clock rates of up to 50 MHz and are compatible with DSP and 1.7 V to 5.5 V digital supply range microcontroller interface standards. Double buffering allows the Asynchronous updating via LDAC asynchronous updating of the DAC output. The input coding Asynchronous RESET to zero scale/midscale is user-selectable twos complement or straight binary. The DSP-/microcontroller-compatible serial interface asynchronous reset function resets all registers to their default Robust 4 kV HBM ESD rating state. The output range is user selectable, via the RA 2:0 bits 16-lead, 3 mm 3 mm LFCSP package in the control register. 16-lead TSSOP package Operating temperature range: 40C to +125C The devices available in a 3 mm 3 mm LFCSP package and a 16-lead TSSOP package offer guaranteed specifications over the APPLICATIONS 40C to +125C industrial temperature range. Industrial automation Instrumentation, data acquisition Open-/closed-loop servo control, process control Programmable logic controllers FUNCTIONAL BLOCK DIAGRAM V V /V DD REFIN REFOUT AD5761R/AD5721R 2.5V REFERENCE DV REFERENCE BUFFERS CC 0V TO 5V ALERT 0V TO 10V SDI 0V TO 16V INPUT SHIFT 12/16 12/16 12-BIT/ SCLK REGISTER INPUT DAC 0V TO 20V V 16-BIT OUT AND REG REG 3V SYNC DAC CONTROL 5V SDO LOGIC 10V RESET 2.5V TO +7.5V CLEAR DNC DGND V LDAC AGND SS NOTES 1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN. Figure 1. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20142018 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 12355-001AD5761R/AD5721R Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Thermal Hysteresis .................................................................... 27 Applications ....................................................................................... 1 Register Details ............................................................................... 28 General Description ......................................................................... 1 Input Shift Register .................................................................... 28 Functional Block Diagram .............................................................. 1 Control Register ......................................................................... 29 Revision History ............................................................................... 2 Readback Control Register ....................................................... 30 Specif icat ions ..................................................................................... 3 Update DAC Register from Input Register ............................. 31 AC Performance Characteristics ................................................ 6 Readback DAC Register ............................................................ 31 Timing Characteristics ................................................................ 7 Write and Update DAC Register .............................................. 31 Timing Diagrams .......................................................................... 7 Readback Input Register ............................................................ 32 Absolute Maximum Ratings ............................................................ 9 Disable Daisy-Chain Functionality .......................................... 32 ESD Caution .................................................................................. 9 Software Data Reset ................................................................... 32 Pin Configurations and Function Descriptions ......................... 10 Software Full Reset ..................................................................... 33 Typical Performance Characterstics............................................. 12 No Operation Registers ............................................................. 33 Terminology .................................................................................... 23 Applications Information .............................................................. 34 Theory of Operation ...................................................................... 25 Typical Operating Circuit ......................................................... 34 Digital-to-Analog Converter .................................................... 25 Power Supply Considerations ................................................... 34 Transfer Function ....................................................................... 25 Evaluation Board ........................................................................ 34 DAC Architecture ....................................................................... 25 Outline Dimensions ....................................................................... 35 Serial Interface ............................................................................ 26 Ordering Guide .......................................................................... 36 Hardware Control Pins .............................................................. 26 REVISION HISTORY 1/2018Rev. B to Rev. C Changes to Figure 35 ...................................................................... 16 Changes to Transfer Function Section ......................................... 25 Changes to Figure 37 ...................................................................... 17 Moved DAC Output Amplifier Section ....................................... 26 Changes to Figure 50 ...................................................................... 19 Change to DB 15:11 Column, Table 11 and RA 2:0 Changes to Figure 58 to Figure 60 ................................................ 20 Description Column, Table 12 ...................................................... 29 Changes to Figure 61 to Figure 66 ................................................ 21 Changes to Figure 69 ...................................................................... 22 Change to DB 15:13 Column, Table 15 ..................................... 30 Updated Outline Dimensions ....................................................... 35 Added Figure 71 ............................................................................. 22 Moved Ordering Guide Section.................................................... 36 Changes to Terminology Section ................................................. 23 Changes to Ordering Guide .......................................................... 36 Changes to Digital-to-Analog Converter Section and Internal Reference Section ........................................................................... 25 10/2016Rev. A to Rev. B CLEAR Changes to Asynchronous Clear Function ( ) Section ....... 27 Changes to Features Section ........................................................... 1 Changes to Table 12 ....................................................................... 29 Changes to Power Supply Considerations Section and 5/2015Rev. 0 to Rev. A Figure 77 .......................................................................................... 34 Added LFCSP Package ....................................................... Universal Added Figure 79 ............................................................................. 35 Changes to Table 1 ............................................................................ 3 Updated Outline Dimensions ....................................................... 35 Changes to Table 2 ............................................................................ 6 Changes to Ordering Guide .......................................................... 35 Changes to Table 4 ............................................................................ 9 Added Figure 6 and Table 6 Renumbered Sequentially ........... 11 11/2014Revision 0: Initial Version Changes to Figure 21 to Figure 24 ................................................ 14 Rev. C Page 2 of 36