Complete, Dual, 12-/14-/16-Bit, Serial Input, Unipolar/Bipolar, Voltage Output DACs Data Sheet AD5722/AD5732/AD5752 FEATURES GENERAL DESCRIPTION Complete, dual, 12-/14-/16-bit digital-to-analog converter (DAC) The AD5722/AD5732/AD5752 are dual, 12-/14-/16-bit, serial Operates from single/dual supplies input, voltage output, digital-to-analog converters. They operate Software programmable output range from single-supply voltages from +4.5 V up to +16.5 V or dual- +5 V, +10 V, +10.8 V, 5 V, 10 V, 10.8 V supply voltages from 4.5 V up to 16.5 V. Nominal full-scale INL error: 16 LSB maximum, DNL error: 1 LSB maximum output range is software-selectable from +5 V, +10 V, +10.8 V, Total unadjusted error (TUE): 0.1% FSR maximum 5 V, 10 V, or 10.8 V. Integrated output amplifiers, reference Settling time: 10 s typical buffers, and proprietary power-up/power-down control circuitry Integrated reference buffers are also provided. Output control during power-up/brownout The parts offer guaranteed monotonicity, integral nonlinearity Simultaneous updating via LDAC (INL) of 16 LSB maximum, low noise, and 10 s typical Asynchronous CLR to zero scale or midscale settling time. DSP-/microcontroller-compatible serial interface The AD5722/AD5732/AD5752 use a serial interface that 24-lead TSSOP operates at clock rates up to 30 MHz and are compatible with Operating temperature range: 40C to +85C 1 DSP and microcontroller interface standards. Double buffering iCMOS process technology allows the simultaneous updating of all DACs. The input coding APPLICATIONS is user-selectable twos complement or offset binary for a bipolar Industrial automation 2sComp output (depending on the state of Pin BIN/ ), and Closed-loop servo control, process control straight binary for a unipolar output. The asynchronous clear Automotive test and measurement function clears all DAC registers to a user-selectable zero-scale Programmable logic controllers or midscale output. The parts are available in a 24-lead TSSOP and offer guaranteed specifications over the 40C to +85C industrial temperature range. The AD5722/AD5732/AD5752 are pin compatible with the AD5724/AD5734/AD5754, which are complete, quad, 12-/14-/ 16-bit, serial input, unipolar/bipolar voltage output DACs. FUNCTIONAL BLOCK DIAGRAM AV AV SS DD REFIN DV CC AD5722/AD5732/AD5752 REFERENCE BUFFERS CLR BIN/2sCOMP 12/14/16 12/14/16 INPUT DAC DAC A SDIN V A REGISTER A REGISTER A OUT INPUT SHIFT REGISTER SCLK AND CONTROL 12/14/16 SYNC INPUT DAC LOGIC DAC B REGISTER B REGISTER B V B OUT SDO DAC GND (2) SIG GND (2) GND LDAC Figure 1. 1 For analog systems designers within industrial/instrumentation equipment OEMs who need high performance ICs at higher voltage levels, iCMOS is a technology platform that enables the development of analog ICs capable of 30 V and operating at 15 V supplies while allowing dramatic reductions in power consumption and package size, as well as increased ac and dc performance. Rev. F Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20082017 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 06467-001AD5722/AD5732/AD5752 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Transfer Function ....................................................................... 20 Applications ....................................................................................... 1 Input Shift Register .................................................................... 24 General Description ......................................................................... 1 DAC Register .............................................................................. 25 Functional Block Diagram .............................................................. 1 Output Range Select Register ................................................... 25 Revision History ............................................................................... 2 Control Register ......................................................................... 26 Specif icat ions ..................................................................................... 3 Power Control Register ............................................................. 26 AC Performance Characteristics ................................................ 5 Design Features ............................................................................... 27 Timing Characteristics ................................................................ 5 Analog Output Control ............................................................. 27 Timing Diagrams .......................................................................... 6 Power-Down Mode .................................................................... 27 Absolute Maximum Ratings ............................................................ 8 Overcurrent Protection ............................................................. 27 ESD Caution .................................................................................. 8 Thermal Shutdown .................................................................... 27 Pin Configuration and Function Descriptions ............................. 9 Applications Information .............................................................. 28 Typical Performance Characteristics ........................................... 10 +5 V/5 V Operation ................................................................ 28 Terminology .................................................................................... 16 Alternative Power-Up Sequence Support ............................... 28 Theory of Operation ...................................................................... 18 Layout Guidelines....................................................................... 28 Architec ture ................................................................................. 18 Galvanically Isolated Interface ................................................. 29 Power-Up Sequence ................................................................... 18 Voltage Reference Selection ...................................................... 29 Serial Interface ............................................................................ 18 Microprocessor Interfacing ....................................................... 29 Load DAC (LDAC ) ..................................................................... 20 Outline Dimensions ....................................................................... 31 Ordering Guide .......................................................................... 31 CLR Asynchronous Clear ( ) ....................................................... 20 Configuring the AD5722/AD5732/AD5752 .......................... 20 REVISION HISTORY 2/2017Rev. E to Rev. F 3/2011Rev. B to Rev. C Added Power-Up Sequence Section ............................................. 18 Changes to Configuring the AD5722/AD5732/AD5752 Section .. 20 Changes to Table 7 and Table 8 ..................................................... 21 Changes to Table 10 and Table 11 ................................................ 22 8/2010Rev. A to Rev. B Changes to Table 13 and Table 14 ................................................ 23 Changes to Table 27 ....................................................................... 26 Changes to Analog Output Control Section ............................... 27 Added Alternative Power-Up Sequence Support Section, 5/2010Rev. 0 to Rev. A Figure 43, and Figure 44 Renumbered Sequentially ................. 28 Changes to Junction Temperature, TJ max Parameter, Table 4 ... 8 Changes to Exposed Paddle Description, Table 5 ......................... 9 2/2016Rev. D to Rev. E Changes to Ordering Guide .......................................................... 30 Changes to Table 1 ............................................................................ 3 10/08Revision 0: Initial Version 7/2011Rev. C to Rev. D Changes to Table 3: t7, t8, t10 Limits ...................................................... 5 Rev. F Page 2 of 31