Complete, Dual, 12-/14-/16-Bit, Serial Input, Unipolar/Bipolar, Voltage Output DACs Data Sheet AD5722R/AD5732R/AD5752R Nominal full-scale output range is software selectable from FEATURES +5 V, +10 V, +10.8 V, 5 V, 10 V, or 10.8 V. Integrated output Complete, dual, 12-/14-/16-bit digital-to-analog converter (DAC) amplifiers, reference buffers, and proprietary power-up/power- Operates from single/dual supplies down control circuitry are also provided. Software programmable output range +5 V, +10 V, +10.8 V, 5 V, 10 V, 10.8 V The devices offer guaranteed monotonicity, integral INL error: 16 LSB maximum, DNL error: 1 LSB maximum nonlinearity (INL) of 16 LSB maximum, low noise, 10 s Total unadjusted error (TUE): 0.1% FSR maximum maximum settling time, and an on-chip +2.5 V reference. Settling time: 10 s typical The AD5722R/AD5732R/AD5752R use a serial interface that Integrated reference: 5 ppm/C maximum operates at clock rates up to 30 MHz and are compatible with Integrated reference buffers DSP and microcontroller interface standards. Double buffering Output control during power-up/brownout allows the simultaneous updating of all DACs. The input coding Simultaneous updating via LDAC is user-selectable twos complement or offset binary for a bipolar Asynchronous CLR to zero scale or midscale 2sComp output (depending on the state of Pin BIN/ ), and DSP-/microcontroller-compatible serial interface straight binary for a unipolar output. The asynchronous clear 24-lead TSSOP function clears all DAC registers to a user-selectable zero-scale Operating temperature range: 40C to +85C 1 or midscale output. The devices are available in a 24-lead iCMOS process technology TSSOP and offer guaranteed specifications over the 40C to APPLICATIONS +85C industrial temperature range. Industrial automation Closed-loop servo control, process control Table 1. Pin Compatible Devices Automotive test and measurement Device Number Description Programmable logic controllers AD5722/AD5732/AD5752 AD5722R/AD5732R/AD5752R without internal reference. GENERAL DESCRIPTION AD5724/AD5734/AD5754 Complete, quad, 12-/14-/16-bit, The AD5722R/AD5732R/AD5752R are dual, 12-/14-/16-bit, serial input, unipolar/bipolar, serial input, voltage output digital-to-analog converters. They voltage output DACs. operate from single supply voltages of +4.5 V up to +16.5 V or AD5724R/AD5734R/AD5754R AD5724/AD5734/AD5754 with dual supply voltages from 4.5 V up to 16.5 V. internal reference FUNCTIONAL BLOCK DIAGRAM AV AV SS DD REFIN/REFOUT AD5722R/AD5732R/AD5752R DV CC 2.5V REFERENCE CLR REFERENCE BUFFERS BIN/2sCOMP n n INPUT DAC DAC A SDIN V A REGISTER A REGISTER A OUT INPUT SHIFT REGISTER SCLK AND CONTROL n SYNC INPUT DAC LOGIC DAC B V B REGISTER B REGISTER B OUT SDO GND LDAC DAC GND (2) SIG GND (2) AD5722: n = 12-BIT AD5732: n = 14-BIT AD5752: n = 16-BIT Figure 1. 1 For analog systems designers within industrial/instrumentation equipment OEMs who need high performance ICs at higher voltage levels, iCMOS is a technology platform that enables the development of analog ICs capable of 30 V and operating at 15 V supplies while allowing dramatic reductions in power consumption and package size, as well as increased ac and dc performance. Rev. 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Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 06466-001AD5722R/AD5732R/AD5752R Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Input Shift Register .................................................................... 26 Applications ....................................................................................... 1 DAC Register .............................................................................. 27 General Description ......................................................................... 1 Output Range Select Register ................................................... 27 Functional Block Diagram .............................................................. 1 Control Register ......................................................................... 28 Revision History ............................................................................... 2 Power Control Register.............................................................. 28 Specifications ..................................................................................... 3 Design Features ............................................................................... 29 AC Performance Characteristics ................................................ 5 Analog Output Control ............................................................. 29 Timing Characteristics ................................................................ 6 Power-Up Sequence ................................................................... 20 Timing Diagrams .......................................................................... 7 Power-Down Mode .................................................................... 29 Absolute Maximum Ratings ............................................................ 9 Overcurrent Protection ............................................................. 29 ESD Caution .................................................................................. 9 Thermal Shutdown .................................................................... 29 Pin Configuration and Function Descriptions ........................... 10 Internal Reference ...................................................................... 29 Typical Performance Characteristics ........................................... 11 Applications Information .............................................................. 30 Terminology .................................................................................... 18 +5 V/5 V Operation ................................................................ 30 Theory of Operation ...................................................................... 20 Layout Guidelines....................................................................... 30 Architecture ................................................................................. 20 Galvanically Isolated Interface ................................................. 31 Serial Interface ............................................................................ 20 Microprocessor Interfacing ....................................................... 31 Load DAC (LDAC)..................................................................... 22 Outline Dimensions ....................................................................... 32 Ordering Guide .......................................................................... 32 CLR Asynchronous Clear ( ) ....................................................... 22 Configuring the AD5722R/AD5732R/AD5752R .................. 22 Transfer Function ....................................................................... 22 REVISION HISTORY 2/2017Rev. E to Rev. F 3/2011Rev. B to Rev. C Added Power-Up Sequence Section ............................................. 20 Changes to Configuring the AD5722R/AD5732R/ Changes to Table 8 and Table 9 ..................................................... 23 AD5752R Section ........................................................................... 22 Changes to Table 11 and Table 12 ................................................ 24 Changes to Table 14 and Table 15 ................................................ 25 8/2010Rev. A to Rev. B Change to Analog Output Section ............................................... 29 Changes to Table 28 ....................................................................... 28 Added Alternative Power-Up Sequence Support Section ......... 30 4/2010Rev. 0 to Rev. A 2/2016Rev. D to Rev. E Changes to Junction Temperature, T max Parameter, Table 5 ... 9 J Changes to Table 1 ............................................................................ 3 Changes to Exposed Paddle Description, Table 6 ...................... 10 7/2011Rev. C to Rev. D 11/2008Revision 0: Initial Version Changes to Table 4: t7, t8, t10 Limits ....................................................... 6 Rev. F Page 2 of 32