Quad, 12-Bit, Parallel Input, Unipolar/Bipolar, Voltage Output DAC Data Sheet AD5725 FEATURES FUNCTIONAL BLOCK DIAGRAM AV AV V +5 V to 15 V operation SS DD REFP Unipolar or bipolar operation V L 12 12 0.5 LSB max INL error, 1 LSB max DNL error INPUT DAC A0 DAC A V OUTA REG A REG A I/O Settling time: 10 s max (10 V step) REGISTER A1 AND Double-buffered inputs 12 R/W CONTROL INPUT DAC DAC B V LOGIC OUTB REG B REG B LDAC CS Simultaneous updating via CLR Asynchronous to zero/mid scale 12 INPUT DAC 12 DAC C V OUTC REG C REG C Readback DB0 TO Operating temperature range: 40C to +85C 12 INPUT DAC DB11 DAC D V OUTD REG D REG D iCMOS process technology AD5725 APPLICATIONS DGND V CLR LDAC REFN Industrial automation Figure 1. Closed-loop servo control, process control Automotive test and measurement Programmable logic controllers GENERAL DESCRIPTION The AD5725 is a quad, 12-bit, parallel input, voltage output Digital controls allow the user to load or read back data from digital-to-analog converter that offers guaranteed monotonicity, any DAC, load any DAC, and transfer data to all DACs at integral nonlinearity (INL) of 0.5 LSB maximum and 10 s one time. maximum settling time. The AD5725 is available in a 28-lead SSOP package. It can be Output voltage swing is set by two reference inputs, V and operated from a wide variety of supply and reference voltages, REFP V . By setting the V input to 0 V and the V to a with supplies ranging from single +5 V to 15 V, and references REFN REFN REFP positive voltage, the DAC provides a unipolar positive output from +2.5 V to 10 V. Power dissipation is less than 270 mW range. A similar configuration with VREFP at 0 V and VREFN at a with 15 V supplies and only 40 mW with a +5 V supply. negative voltage provides a unipolar negative output range. Operation is specified over the temperature range of 40C Bipolar outputs are configured by connecting both VREFP and to +85C. VREFN to nonzero voltages. This method of setting output voltage ranges has advantages over the bipolar offsetting methods because it is not dependent on internal and external resistors with different temperature coefficients. iCMOS Process Technology For analog systems designers within industrial/instrumentation equipment OEMs who need high performance ICs at higher-voltage levels, iCMOS is a technology platform that enables the development of analog ICs capable of 30 V and operating at 15 V supplies while allowing dramatic reductions in power consumption and package size, and increased ac and dc performance. Rev. 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Technical Support www.analog.com 06442-001AD5725 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 15 Applications ....................................................................................... 1 DAC Architecture....................................................................... 15 Functional Block Diagram .............................................................. 1 Output Amplifiers ...................................................................... 15 General Description ......................................................................... 1 Reference Inputs ......................................................................... 15 Revision History ............................................................................... 2 Parallel Interface ......................................................................... 15 Specifications ..................................................................................... 3 Data Coding ................................................................................ 15 AC Performance Characteristics ................................................ 5 CLR ............................................................................................... 15 , Timing Characteristics ............................................................... 6 Power Supplies ............................................................................ 17 Absolute Maximum Ratings ............................................................ 8 Reference Configuration ........................................................... 17 ESD Caution .................................................................................. 8 Single +5 V Supply Operation .................................................. 18 Pin Configuration and Function Descriptions ............................. 9 Outline Dimensions ....................................................................... 19 Typical Performance Characteristics ........................................... 10 Ordering Guide .......................................................................... 19 Terminology .................................................................................... 14 REVISION HISTORY 8/13Rev. B to Rev. C Change Junction Temperature from 105C to 150C Changed Power Dissipation Package Condition from Derate 10 mW/C Above 70C to Derate 10 mW/C Above 60C Table 5 .............. 8 4/13Rev. A to Rev. B Changes to VREFN Input Current Parameter, Table 1 .................... 3 Changes to Figure 27 and Figure 28 ............................................. 17 Changes to Figure 29 and Figure 30 ............................................. 18 12/08Rev. 0 to Rev. A Changes to Figure 26 ...................................................................... 13 7/07Revision 0: Initial Version Power Dissipation Package (Derate 10 mW/C Above 60C) Rev. C Page 2 of 20