Quad-Channel, 12-Bit, Serial Input, 4 mA to 20 mA and Voltage Output DAC with Dynamic Power Control Data Sheet AD5735 On-chip dynamic power control minimizes package power FEATURES dissipation in current mode. This reduced power dissipation 12-bit resolution and monotonicity is achieved by regulating the voltage on the output driver from Dynamic power control for thermal management 7.4 V to 29.5 V using a dc-to-dc boost converter optimized for Current and voltage output pins connectable to a single minimum on-chip power dissipation. terminal Current output ranges: 0 mA to 20 mA, 4 mA to 20 mA, The AD5735 uses a versatile 3-wire serial interface that operates and 0 mA to 24 mA at clock rates of up to 30 MHz and is compatible with standard 0.1% total unadjusted error (TUE) maximum SPI, QSPI, MICROWIRE, DSP, and microcontroller interface Voltage output ranges (with 20% overrange): 0 V to 5 V, standards. The serial interface also features optional CRC-8 packet 0 V to 10 V, 5 V, and 10 V error checking, as well as a watchdog timer that monitors activity 0.09% total unadjusted error (TUE) maximum on the interface. User-programmable offset and gain PRODUCT HIGHLIGHTS On-chip diagnostics 1. Dynamic power control for thermal management. On-chip reference: 10 ppm/C maximum 2. 12-bit performance. 40C to +105C temperature range 3. Quad channel. APPLICATIONS COMPANION PRODUCTS Process control Product Family: AD5755, AD5755-1, AD5757, AD5737 Actuator control External References: ADR445, ADR02 PLCs Digital Isolators: ADuM1410, ADuM1411 GENERAL DESCRIPTION Power: ADP2302, ADP2303 The AD5735 is a quad-channel voltage and current output DAC Additional companion products on the AD5735 product page that operates with a power supply range from 26.4 V to +33 V. FUNCTIONAL BLOCK DIAGRAM AV CC 5.0V AV AV SS DD 15V AGND +15V SW V x BOOST x DV 7.4V TO 29.5V DD DGND DC-TO-DC LDAC CONVERTER SCLK SDIN DIGITAL SYNC I OUT x INTERFACE SDO R + DAC A SET x CLEAR CURRENT AND VOLTAGE FAULT OUTPUT RANGE SCALING ALERT GAIN REG A +V SENSE x AD1 OFFSET REG A V OUT x AD0 V DAC CHANNEL A SENSE x REFOUT REFERENCE REFIN DAC CHANNEL B DAC CHANNEL C AD5735 DAC CHANNEL D NOTES 1. x = A, B, C, OR D. Figure 1. Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20112017 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. 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Technical Support www.analog.com 09961-100AD5735 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Data Registers ............................................................................. 33 Applications ....................................................................................... 1 Control Registers ........................................................................ 35 General Description ......................................................................... 1 Readback Operation .................................................................. 38 Product Highlights ........................................................................... 1 Device Features ............................................................................... 40 Companion Products ....................................................................... 1 Fault Output ................................................................................ 40 Functional Block Diagram .............................................................. 1 Voltage Output Short-Circuit Protection ................................ 40 Revision History ............................................................................... 3 Digital Offset and Gain Control ............................................... 40 Detailed Functional Block Diagram .............................................. 4 Status Readback During a Write .............................................. 40 Specifications ..................................................................................... 5 Asynchronous Clear ................................................................... 41 AC Performance Characteristics ................................................ 8 Packet Error Checking ............................................................... 41 Timing Characteristics ................................................................ 9 Watchdog Timer ......................................................................... 41 Absolute Maximum Ratings .......................................................... 12 Alert Output ................................................................................ 41 Thermal Resistance .................................................................... 12 Internal Reference ...................................................................... 41 ESD Caution ................................................................................ 12 External Current Setting Resistor ............................................ 42 Pin Configuration and Function Descriptions ........................... 13 Digital Slew Rate Control .......................................................... 42 Typical Performance Characteristics ........................................... 16 Dynamic Power Control............................................................ 43 Voltage Outputs .......................................................................... 16 DC-to-DC Converters ............................................................... 43 Current Outputs ......................................................................... 20 AICC Supply RequirementsStatic .......................................... 44 DC-to-DC Converter ................................................................. 24 AICC Supply RequirementsSlewing ...................................... 44 Reference ..................................................................................... 25 Applications Information .............................................................. 46 General ......................................................................................... 26 Voltage and Current Output Pins on the Same Terminal ..... 46 Terminology .................................................................................... 27 Current Output Mode with Internal R ................................ 46 SET Theory of Operation ...................................................................... 29 Precision Voltage Reference Selection ..................................... 46 DAC Architecture ....................................................................... 29 Driving Inductive Loads ............................................................ 47 Power-On State of the AD5735 ................................................ 30 Transient Voltage Protection .................................................... 47 Serial Interface ............................................................................ 30 Microprocessor Interfacing ....................................................... 47 Transfer Function ....................................................................... 30 Layout Guidelines....................................................................... 47 Registers ........................................................................................... 31 Galvanically Isolated Interface ................................................. 48 Enabling the Output ................................................................... 32 Outline Dimensions ....................................................................... 49 Reprogramming the Output Range ......................................... 32 Ordering Guide .......................................................................... 49 Rev. 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