Complete, Quad, 12-/14-/16-Bit, Serial Input, Unipolar/Bipolar Voltage Output DACs Data Sheet AD5724/AD5734/AD5754 FEATURES GENERAL DESCRIPTION Complete, quad, 12-/14-/16-bit digital-to-analog The AD5724/AD5734/AD5754 are quad, 12-/14-/16-bit, serial converter (DAC) input, voltage output DACs. The devices operate from single- Operates from single/dual supplies supply voltages from +4.5 V up to +16.5 V or dual-supply Software programmable output range voltages from 4.5 V up to 16.5 V. Nominal full-scale output +5 V, +10 V, +10.8 V, 5 V, 10 V, 10.8 V range is software-selectable from +5 V, +10 V, +10.8 V, 5 V, INL error: 16 LSB maximum, DNL error: 1 LSB maximum 10 V, or 10.8 V. Integrated output amplifiers, reference buffers, Total unadjusted error (TUE): 0.1% FSR maximum and proprietary power-up/power-down control circuitry are also Settling time: 10 s typical provided. Integrated reference buffers The devices offer guaranteed monotonicity, integral Output control during power-up/brownout nonlinearity (INL) of 16 LSB maximum, low noise, and 10 s Simultaneous updating via LDAC maximum settling time. Asynchronous CLR to zero scale or midscale The AD5724/AD5734/AD5754 use a serial interface that operates DSP-/microcontroller-compatible serial interface at clock rates up to 30 MHz and are compatible with DSP and 24-lead TSSOP microcontroller interface standards. Double buffering allows Operating temperature range: 40C to +85C 1 the simultaneous updating of all DACs. The input coding is iCMOS process technology user-selectable twos complement or offset binary for a bipolar APPLICATIONS output (depending on the state of Pin BIN/2sComp), and straight Industrial automation binary for a unipolar output. The asynchronous clear function Closed-loop servo control, process control clears all DAC registers to a user-selectable zero-scale or midscale Automotive test and measurement output. The devices are available in a 24-lead TSSOP and offer Programmable logic controllers guaranteed specifications over the 40C to +85C industrial temperature range. FUNCTIONAL BLOCK DIAGRAM AV AV SS DD REFIN DV CC AD5724/AD5734/AD5754 REFERENCE BUFFERS n n INPUT DAC DAC A SDIN V A REGISTER A REGISTER A OUT INPUT SHIFT REGISTER SCLK AND n CONTROL SYNC INPUT DAC LOGIC DAC B V B REGISTER B REGISTER B OUT SDO n INPUT DAC DAC C REGISTER C REGISTER C V C OUT CLR BIN/2sCOMP n INPUT DAC DAC D V D OUT REGISTER D REGISTER D AD5724: n = 12-BIT GND LDAC DAC GND (2) SIG GND (2) AD5734: n = 14-BIT AD5754: n = 16-BIT Figure 1. 1 For analog systems designers within industrial/instrumentation equipment OEMs that need high performance ICs at higher-voltage levels, iCMOS is a technology platform that enables the development of analog ICs capable of 30 V and operating at 15 V supplies while allowing dramatic reductions in power consumption and package size, as well as increased ac and dc performance. Rev. F Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20082017 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com 06468-001AD5724/AD5734/AD5754 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Transfer Function ....................................................................... 20 Applications ....................................................................................... 1 Input Shift Register .................................................................... 24 General Description ......................................................................... 1 DAC Register .............................................................................. 24 Functional Block Diagram .............................................................. 1 Output Range Select Register ................................................... 25 Revision History ............................................................................... 2 Control Register ......................................................................... 25 Specifications ..................................................................................... 3 Power Control Register.............................................................. 26 AC Performance Characteristics ................................................ 5 Features ............................................................................................ 27 Timing Characteristics ................................................................ 5 Analog Output Control ............................................................. 27 Timing Diagrams .......................................................................... 6 Power-Down Mode .................................................................... 27 Absolute Maximum Ratings ............................................................ 8 Overcurrent Protection ............................................................. 27 ESD Caution .................................................................................. 8 Thermal Shutdown .................................................................... 27 Pin Configuration and Function Descriptions ............................. 9 Applications Information .............................................................. 28 Typical Performance Characteristics ........................................... 10 +5 V/5 V Operation ................................................................ 28 Terminology .................................................................................... 16 Alternative Power-Up Sequence Support ............................... 28 Theory of Operation ...................................................................... 18 Layout Guidelines....................................................................... 28 Architecture ................................................................................. 18 Galvanically Isolated Interface ................................................. 29 Power-Up Sequence ................................................................... 18 Voltage Reference Selection ...................................................... 29 Serial Interface ............................................................................ 18 Microprocessor Interfacing ....................................................... 29 LDAC Outline Dimensions ....................................................................... 31 Load DAC ( )..................................................................... 20 Ordering Guide .......................................................................... 31 CLR Asynchronous Clear ( ) ....................................................... 20 Configuring the AD5724/AD5734/AD5754 .......................... 20 REVISION HISTORY 2/2017Rev. E to Rev. F Added Power-Up Sequence Section ............................................. 18 3/2011Rev. B to Rev. C Changes to Table 7 and Table 8 ..................................................... 21 Changes to Configuring the AD5724/AD5734/AD5754 Changes to Table 10 and Table 11 ................................................ 22 Section .............................................................................................. 20 Changes to Table 13 and Table 14 ................................................ 23 Changes to Analog Output Control Section ............................... 27 8/2010Rev. A to Rev. B Added Alternative Power-Up Sequence Support Section, Changes to Table 27 ....................................................................... 26 Figure 43, and Figure 44 Renumbered Sequentially ................. 28 4/2010Rev. 0 to Rev. A 2/2016Rev. D to Rev. E Changes to Junction Temperature, T max Parameter, Table 4 ... 8 J Changes to Table 1...................................................................................... 3 Changes to Exposed Pad Description, Table 5 .............................. 9 Change to Table 5 ......................................................................................... 9 Added Exposed Paddle Notation to Outline Dimensions ........ 30 7/2011Rev. C to Rev. D 8/2008Revision 0: Initial Version Changes to Table 3: t7, t8, t10 Limits ....................................................... 5 Rev. F Page 2 of 31