Ultra Stable, 16-Bit 0.5 LSB INL, Voltage Output DAC Data Sheet AD5760 FEATURES FUNCTIONAL BLOCK DIAGRAM V V V CC DD REFP True 16-bit voltage output DAC, 0.5 LSB INL 8 nV/Hz output noise spectral density 6.8k 6.8k 0.00625 LSB long-term linearity error stability A1 R IOV CC FB R1 R FB 0.018 ppm/C gain error temperature coefficient INV SDIN INPUT 2.5 s output voltage settling time 16 16 SHIFT 16-BIT DAC SCLK V OUT REGISTER DAC REG 3.5 nV-sec midscale glitch impulse AND SYNC CONTROL Integrated precision reference buffers LOGIC SDO Operating temperature range: 40C to +125C 6k LDAC 4 mm 5 mm LFCSP package CLR POWER-ON RESET Wide power supply range of up to 16.5 V AND CLEAR LOGIC RESET AD5760 35 MHz Schmitt triggered digital interface 1.8 V-compatible digital interface DGND V AGND V SS REFN Figure 1. APPLICATIONS Medical instrumentation Test and measurement Table 1. Related Devices Industrial control Part No. Description Scientific and aerospace instrumentation AD5790 20-bit, 2 LSB accurate DAC Data acquisition systems AD5791 20-bit, 1 LSB accurate DAC Digital gain and offset adjustment AD5780 18-bit, 1 LSB accurate DAC Power supply control AD5781 18-bit, 0.5 LSB INL AD5541A/AD5542A 16-bit, 1 LSB accurate 5 V DAC GENERAL DESCRIPTION 1 The AD5760 is a true 16-bit, unbuffered voltage output digital- PRODUCT HIGHLIGHTS to-analog converter (DAC) that operates from a bipolar supply 1. True 16-bit accuracy. of up to 33 V. The AD5760 accepts a positive reference input 2. Wide power supply range of up to 16.5 V. range of 5 V to VDD 2.5 Vand a negative reference input range 3. 40C to +125C operating temperature range. of VSS + 2.5 V to 0 V. The AD5760 offers a relative accuracy 4. Low 8 nV/Hz noise. specification of 0.5 LSB maximum range, and operation is 5. Low 0.018 ppm/C gain error temperature coefficient. guaranteed monotonic with a 0.5 LSB differential nonlinearity (DNL) maximum range specification. COMPANION PRODUCTS Output Amplifier Buffer: AD8675, ADA4898-1, ADA4004-1 The device uses a versatile 3-wire serial interface that operates at clock rates of up to 35 MHz and is compatible with standard External Reference: ADR445 serial peripheral interface (SPI), QSPI, MICROWIRE, and DC-to-DC Design Tool: ADIsimPower DSP interface standards. The device incorporates a power-on Additional companion products on the AD5780 product page. reset circuit that ensures that the DAC output powers up to 0 V in a known output impedance state and remains in this state until a valid write to the device takes place. The device provides an output clamp feature that places the output in a defined load state. 1 Protected by U.S. Patent No. 7,884,747 and 8,089,380. Rev. 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Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 09650-001AD5760 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 DAC Architecture ....................................................................... 18 Applications ....................................................................................... 1 Serial Interface ............................................................................ 18 Functional Block Diagram .............................................................. 1 Hardware Control Pins .............................................................. 19 General Description ......................................................................... 1 On-Chip Registers ...................................................................... 19 Product Highlights ........................................................................... 1 AD5760 Features ............................................................................ 23 Companion Products ....................................................................... 1 Power-On to 0 V ......................................................................... 23 Revision History ............................................................................... 2 Power-Up Sequence ................................................................... 23 Specifications ..................................................................................... 3 Configuring the AD5760 .......................................................... 23 Timing Characteristics ................................................................ 5 DAC Output State ...................................................................... 23 Absolute Maximum Ratings ............................................................ 7 Output Amplifier Configuration.............................................. 23 ESD Caution .................................................................................. 7 Applications Information .............................................................. 25 Pin Configuration and Function Descriptions ............................. 8 Typical Operating Circuit ......................................................... 25 Typical Performance Characteristics ............................................. 9 Evaluation Board ........................................................................ 26 Terminology .................................................................................... 17 Outline Dimensions ....................................................................... 27 Theory of Operation ...................................................................... 18 Ordering Guide .......................................................................... 27 REVISION HISTORY 4/2018Rev. E to Rev. F 9/2012Rev. B to Rev. C Added Power-Up Sequence Section and Figure 50 Renumbered Changes to Patent Footnote ............................................................. 1 Changes to Figure 46 ...................................................................... 17 Sequentially ..................................................................................... 23 Updated Outline Dimensions ....................................................... 27 Changes to Terminology Section ................................................. 19 Changes to Ordering Guide .......................................................... 27 Changes to Figure 53 ...................................................................... 25 Changes to Figure 55 ...................................................................... 27 10/2016Rev. D to Rev. E Updated Outline Dimensions and changes to Changes to Figure 4 and Table 5 ..................................................... 8 Ordering Guide ............................................................................... 29 Changes to Figure 42, Figure 43, and Figure 44 ......................... 15 2/2012Rev. A to Rev. B 7/2013Rev. C to Rev. D Deleted Linearity Compensation Section ...................................... 3 Changes to t1 Test Conditions/Comments and Endnote 2 ......... 5 Deleted Figure 4 ................................................................................ 7 12/2011Rev. 0 to Rev. A Changes to Pin 11 Description ....................................................... 8 Changes to Table 2 ............................................................................. 3 Deleted Daisy-Chain Operation Section ..................................... 20 Changes to Figure 48 ...................................................................... 18 Changes to DAC Register Section ................................................ 22 Changes to Table 10 and Table 11 ................................................ 23 11/2011Revision 0: Initial Version Rev. F Page 2 of 27