Multiple Range, 16-/12-Bit, Bipolar/Unipolar, Voltage Output DACs Data Sheet AD5761/AD5721 FEATURES GENERAL DESCRIPTION 8 software-programmable output ranges: 0 V to +5 V, 0 V to The AD5761/AD5721 are single channel, 16-/12-bit serial input, +10 V, 0 V to +16 V, 0 V to +20 V, 3 V, 5 V, 10 V, 2.5 V to voltage output, digital-to-analog converters (DACs). They operate +7.5 V 5% overrange from single supply voltages from +4.75 V to +30 V or dual Total unadjusted error (TUE): 0.1% FSR maximum supply voltages from 16.5 V to 0 V VSS and +4.75 V to +16.5 V 16-bit resolution: 2 LSB maximum INL VDD. The integrated output amplifier and reference buffer Guaranteed monotonicity: 1 LSB maximum provide a very easy to use, universal solution. Single channel, 16-/12-bit DACs The devices offer guaranteed monotonicity, integral nonlinearity Settling time: 7.5 s typical (INL) of 2 LSB maximum, 35 nV/Hz noise, and 7.5 s settling Integrated reference buffers time on selected ranges. Low noise: 35 nV/Hz The AD5761/AD5721 use a serial interface that operates at Low glitch: 1 nV-sec clock rates of up to 50 MHz and are compatible with DSP and 1.8 V logic compatibility microcontroller interface standards. Double buffering allows Asynchronous updating via LDAC the asynchronous updating of the DAC output. The input Asynchronous RESET to zero scale/midscale coding is user-selectable twos complement or straight binary. DSP/microcontroller-compatible serial interface The asynchronous reset function resets all registers to their Robust 4 kV HBM ESD rating default state. The output range is user selectable, via the Available in 16-lead TSSOP and 16-lead LFCSP RA 2:0 bits in the control register. Operating temperature range: 40C to +125C The devices available in the 16-lead TSSOP and in the 16-lead APPLICATIONS LFCSP offer guaranteed specifications over the 40C to +125C Industrial automation industrial temperature range. Instrumentation, data acquisition Open-/closed-loop servo control, process control Table 1. Pin-Compatible Devices Programmable logic controllers Device Description AD5761R/AD5721R AD5761/AD5721 with internal reference FUNCTIONAL BLOCK DIAGRAM V V DD REFIN AD5761/AD5721 REFERENCE DV BUFFERS CC 0V TO 5V ALERT 0V TO 10V 0V TO 16V SDI INPUT SHIFT 12/16 12/16 12-BIT/ 0V TO 20V SCLK REGISTER INPUT DAC V 16-BIT OUT 3V AND REG REG SYNC DAC CONTROL 5V SDO LOGIC 10V 2.5V TO +7.5V RESET CLEAR DNC DGND V LDAC AGND SS NOTES 1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN. Figure 1. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20152018 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 12640-001AD5761/AD5721 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Register Details ............................................................................... 24 Applications ....................................................................................... 1 Input Shift Register .................................................................... 24 General Description ......................................................................... 1 Control Register ......................................................................... 24 Functional Block Diagram .............................................................. 1 Readback Control Register ....................................................... 26 Revision History ............................................................................... 2 Update DAC Register from Input Register ............................. 26 Specif icat ions ..................................................................................... 3 Readback DAC Register ............................................................ 26 AC Performance Characteristics ................................................ 5 Write and Update DAC Register .............................................. 27 Timing Characteristics ................................................................ 6 Readback Input Register ............................................................ 27 Absolute Maximum Ratings ............................................................ 8 Disable Daisy-Chain Functionality .......................................... 27 ESD Caution .................................................................................. 8 Software Data Reset ................................................................... 28 Pin Configurations and Function Descriptions ........................... 9 Software Full Reset ..................................................................... 28 Typical Performance Characterstics............................................. 10 No Operation Registers ............................................................. 28 Terminology .................................................................................... 20 Applications Information .............................................................. 29 Theory of Operation ...................................................................... 21 Typical Operating Circuit ......................................................... 29 Digital-to-Analog Converter .................................................... 21 Power Supply Considerations ................................................... 29 Transfer Function ....................................................................... 21 Evaluation Board ........................................................................ 29 DAC Architecture ....................................................................... 21 Outline Dimensions ....................................................................... 31 Serial Interface ............................................................................ 22 Ordering Guide .......................................................................... 31 Hardware Control Pins .............................................................. 22 REVISION HISTORY 1/2018Rev. B to Rev. C 5/2015Rev. 0 to Rev. A Changes to Transfer Function Section ......................................... 21 Added 16-Lead LFCSP Package ....................................... Universal Change to DB 15:11 Column, Table 11 ..................................... 24 Added Grade A Parameter, Table 2 ................................................. 3 Change to RA 2:0 Description, Table 12 ................................... 25 Added Figure 5, Renumbered Sequentially ................................... 9 Change to DB 15:13 Column, Table 15 ..................................... 26 Changes to Table 6 ............................................................................. 9 Updated Outline Dimensions ....................................................... 31 Changes to Figure 49 ...................................................................... 17 Changes to Ordering Guide .......................................................... 31 Changes to Power Supply Considerations Section .................... 30 Updated Outline Dimensions ....................................................... 32 4/2016Rev. A to Rev. B Changes to Ordering Guide .......................................................... 32 Changes to Features Section............................................................ 1 Changes to Typical Operating Circuit Section and Precision 1/2015Revision 0: Initial Version Voltage Reference Section ............................................................. 29 Rev. C Page 2 of 31