Complete Dual, 16-Bit, High Accuracy, Serial Input, Bipolar Voltage Output DAC Data Sheet AD5762R FEATURES GENERAL DESCRIPTION Complete dual, 16-bit, digital-to-analog converter (DAC) The AD5762R is a dual, 16-bit, serial input, bipolar voltage output Programmable output range: 10 V, 10.2564 V, or 10.5263 V DAC that operates from supply voltages of 11.4 V to 16.5 V. 1 LSB maximum INL error, 1 LSB maximum DNL error Nominal full-scale output range is 10 V. The AD5762R provides Low noise: 60 nV/Hz integrated output amplifiers, reference buffers, and proprietary Settling time: 10 s maximum power-up/power-down control circuitry. The device also features a Integrated reference buffers digital input/output port, programmed via the serial interface, Internal reference: 10 ppm/C maximum and an analog temperature sensor. The device incorporates On-chip die temperature sensor digital offset and gain adjust registers per channel. Output control during power-up/brownout The AD5762R is a high performance converter that provides Programmable short-circuit protection guaranteed monotonicity, an integral nonlinearity (INL) of LDAC Simultaneous updating via 1 LSB, low noise, and a 10 s settling time. The AD5762R CLR Asynchronous to zero code includes an on-chip 5 V reference with a reference temperature Digital offset and gain adjust coefficient of 10 ppm/C maximum. During power-up when the Logic output control pins supply voltages are changing, VOUTx is clamped to 0 V via a low DSP-/microcontroller-compatible serial interface impedance path. Temperature range: 40C to +85C The AD5762R is based on the iCMOS technology platform, which Industrial complementary metal-oxide semiconductor is designed for analog systems designers within industrial/instru- (iCMOS) process technology mentation equipment original equipment manufacturers (OEMs) APPLICATIONS who need high performance ICs at higher voltage levels. iCMOS Industrial automation enables the development of analog ICs capable of 30 V and Open-loop/closed-loop servo control operation at 15 V supplies, while allowing reductions in power Process control consumption and package size coupled with increased ac and dc Data acquisition systems performance. Automatic test equipment The AD5762R uses a serial interface that operates at clock rates Automotive test and measurement of up to 30 MHz and is compatible with DSP and microcontroller High accuracy instrumentation interface standards. Double buffering allows the simultaneous updating of all DACs. The input coding is programmable to either twos complement or offset binary formats. The asynchronous clear function clears all DAC registers to either bipolar zero or zero scale, depending on the coding used. The AD5762R is ideal for both closed-loop servo control and open-loop control applications. The AD5762R is available in a 32-lead TQFP and offers guaranteed specifications over the 40C to +85C industrial temperature range (see Figure 1 for the functional block diagram). Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20082016 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. AD5762R Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Function Register ....................................................................... 24 Applications ....................................................................................... 1 Data Register ............................................................................... 25 General Description ......................................................................... 1 Coarse Gain Register ................................................................. 25 Revision History ............................................................................... 2 Fine Gain Register ...................................................................... 25 Functional Block Diagram .............................................................. 3 Offset Register ............................................................................ 26 Specifications ..................................................................................... 4 Offset and Gain Adjustment Worked Example ......................... 26 AC Performance Characteristics ................................................ 6 Design Features ............................................................................... 27 Timing Characteristics ................................................................ 7 Analog Output Control ............................................................. 27 Absolute Maximum Ratings .......................................................... 10 Digital Offset and Gain Control ............................................... 27 Thermal Resistance .................................................................... 10 Programmable Short-Circuit Protection ................................ 27 ESD Caution ................................................................................ 10 Digital I/O Port ........................................................................... 27 Pin Configuration and Function Descriptions ........................... 11 Die Temperature Sensor ............................................................ 27 Typical Performance Characteristics ........................................... 13 Local Ground Offset Adjust ...................................................... 27 Terminology .................................................................................... 19 Applications Information .............................................................. 28 Theory of Operation ...................................................................... 21 Typical Operating Circuit ......................................................... 28 DAC Architecture ....................................................................... 21 Layout Guidelines ........................................................................... 30 Reference Buffers ........................................................................ 21 Galvanically Isolated Interface ................................................. 30 Serial Interface ............................................................................ 21 Microprocessor Interfacing ....................................................... 30 Simultaneous Updating via LDAC ........................................... 22 Evaluation Board ........................................................................ 31 Outline Dimensions ....................................................................... 32 Transfer Function ....................................................................... 23 Ordering Guide .......................................................................... 32 CLR Asynchronous Clear ( ) ....................................................... 23 Registers ........................................................................................... 24 REVISION HISTORY 6/2016Rev. C to Rev. D 8/2009Rev. 0 to Rev. A Changes to Table 7 and Table 8 ..................................................... 23 Deleted Endnote 1, Table 1 .............................................................. 4 Deleted Endnote 1, Table 2 .............................................................. 6 9/2011Rev. B to Rev. C Deleted Endnote 1, Table 3 .............................................................. 7 Changed 50 MHz to 30 MHz Throughout.................................... 1 Changes to t6 Parameter, Table 3 ..................................................... 7 Changes to t1, t2, and t3 Parameters, Table 3 .................................. 7 12/2008Revision 0: Initial Version 7/2011Rev. A to Rev. B Changed 30 MHz to 50 MHz Throughout.................................... 1 Changes to t , t , and t Parameters, Table 3 .................................. 7 1 2 3 Rev. D Page 2 of 32