True 18-Bit, Voltage Output DAC 0.5 LSB INL, 0.5 LSB DNL Data Sheet AD5781 FEATURES FUNCTIONAL BLOCK DIAGRAM V V V V CC DD REFPF REFPS Single 18-bit DAC, 0.5 LSB INL 7.5 nV/Hz noise spectral density 6.8k 6.8k AD5781 0.05 LSB long-term linearity stability A1 IOV R CC FB R1 R FB <0.05 ppm/C temperature drift INV SDIN INPUT 1 s settling time 18 18 SHIFT DAC 18-BIT SCLK V OUT REGISTER DAC REG 1.4 nV-sec glitch impulse AND SYNC CONTROL Operating temperature range: 40C to +125C LOGIC SDO 20-lead TSSOP package 6k LDAC Wide power supply range of up to 16.5 V CLR 35 MHz Schmitt triggered digital interface POWER-ON-RESET AND CLEAR LOGIC RESET 1.8 V compatible digital interface DGND V AGND V V SS REFNF REFNS APPLICATIONS Figure 1. Medical instrumentation Test and measurement Industrial control Scientific and aerospace instrumentation Data acquisition systems Digital gain and offset adjustment Power supply control GENERAL DESCRIPTION 1 The AD5781 is a single 18-bit, unbuffered voltage output digital- PRODUCT HIGHLIGHTS to-analog converter (DAC) that operates from a bipolar supply of 1. True 18-Bit Accuracy. up to 33 V. The AD5781 accepts a positive reference input range 2. Wide Power Supply Range of Up to 16.5 V. of 5 V to VDD 2.5 V and a negative reference input range of VSS 3. 40C to +125C Operating Temperature Range. + 2.5 V to 0 V. The AD5781 offers a relative accuracy specifi- 4. Low 7.5 nV/Hz Noise. cation of 0.5 LSB maximum, and operation is guaranteed 5. Low 0.05 ppm/C Temperature Drift. monotonic with a 0.5 LSB differential nonlinearity (DNL) maximum specification. Table 1. Complementary Devices Part No. Description The part uses a versatile 3-wire serial interface that operates at AD8675 Ultraprecision, 36 V, 2.8 nV/Hz rail-to-rail clock rates of up to 35 MHz and is compatible with standard output op amp serial peripheral interface (SPI), QSPI, MICROWIRE, and AD8676 Ultraprecision, 36 V, 2.8 nV/Hz dual rail-to- DSP interface standards. The part incorporates a power-on rail output op amp reset circuit that ensures that the DAC output powers up to 0 V ADA4898-1 High voltage, low noise, low distortion, unity and in a known output impedance state and remains in this state gain stable, high speed op amp until a valid write to the device takes place. The part provides an output clamp feature that places the output in a defined load Table 2. Related Devices state. Part No. Description AD5791 20-bit, 1 ppm accurate DAC AD5541A/AD5542A 16-bit, 1 LSB accurate 5 V DAC 1 Protected by U.S. Patent No 7,884,747, and other patents are pending. Rev. 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Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 09092-001AD5781 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Hardware Control Pins .............................................................. 20 Applications ....................................................................................... 1 On-Chip Registers ...................................................................... 21 Functional Block Diagram .............................................................. 1 AD5781 Features ............................................................................ 24 General Description ......................................................................... 1 Power-On to 0 V ......................................................................... 24 Product Highlights ........................................................................... 1 Power-Up Sequence ................................................................... 24 Revision History ............................................................................... 2 Configuring the AD5781 .......................................................... 24 Specifications ..................................................................................... 3 DAC Output State ...................................................................... 24 Timing Characteristics ................................................................ 5 Linearity Compensation ............................................................ 24 Absolute Maximum Ratings ............................................................ 7 Output Amplifier Configuration.............................................. 24 ESD Caution .................................................................................. 7 Applications Information .............................................................. 26 Pin Configuration and Function Description .............................. 8 Typical Operating Circuit ......................................................... 26 Typical Performance Characteristics ............................................. 9 Evaluation Board ........................................................................ 26 Terminology .................................................................................... 17 Outline Dimensions ....................................................................... 27 Theory of Operation ...................................................................... 19 Ordering Guide .......................................................................... 27 DAC Architecture ....................................................................... 19 REVISION HISTORY 4/2018Rev. D to Rev. E 8/2011Rev. 0 to Rev. A Added Power-Up Sequence Section and Figure 50 Renumbered Change to Features Section .............................................................. 1 Changes to Specifications Section ................................................... 3 Sequentially ..................................................................................... 24 Deleted t14 Parameter from Timing Specifications Section, 7/2013Rev. C to Rev. D Table 4 .................................................................................................5 Changes to t1 Test Conditions/Comments and Endnote 2 ......... 5 Changes to Figure 2 and Figure 3 .................................................... 6 Deleted Figure 4 ................................................................................ 7 Changes to Figure 4 ........................................................................... 7 Deleted Daisy-Chain Operation Section ..................................... 20 Replaced Figure 42 and Figure 43 ................................................ 16 Added New Figure 44, Figure 45, and Figure 46, Renumbered 11/2011Rev. B to Rev. C Sequentially ..................................................................................... 16 Added Figure 48 Renumbered Sequentially .............................. 17 Change to Ideal Transfer Function Equation .............................. 22 7/2010Revision 0: Initial Version 9/2011Rev. A to Rev. B Added Patent Note ........................................................................... 1 Changes to Table 3 ............................................................................ 3 Changes to OPGND Description, Table 12 ................................ 23 Rev. E Page 2 of 27