System Ready, 20-Bit, 2 LSB INL, Voltage Output DAC Data Sheet AD5790 FEATURES FUNCTIONAL BLOCK DIAGRAM V V V CC DD REFP Single 20-bit voltage output DAC, 2 LSB INL 8 nV/Hz output noise spectral density 6.8k 6.8k A1 0.1 LSB long-term linearity error stability IOV R CC FB R1 R FB 0.018 ppm/C gain error temperature coefficient INV SDIN INPUT 20 20 2.5 s output voltage settling time SHIFT 20-BIT DAC SCLK V OUT REGISTER DAC REG 3.5 nV-sec midscale glitch impulse AND SYNC CONTROL LOGIC Integrated precision reference buffers SDO 6k Operating temperature range: 40C to +125C LDAC 4 mm 5 mm LFCSP package CLR POWER-ON-RESET Wide power supply range of up to 16.5 V AND CLEAR LOGIC RESET AD5790 35 MHz Schmitt-triggered digital interface DGND V AGND V SS REFN 1.8 V compatible digital interface Figure 1. APPLICATIONS Medical instrumentation Test and measurement Industrial control Scientific and aerospace instrumentation Data acquisition systems Digital gain and offset adjustment Power supply control GENERAL DESCRIPTION 1 The AD5790 is a single, 20-bit, unbuffered voltage output digital- PRODUCT HIGHLIGHTS to-analog converter (DAC) that operates from a bipolar supply of 1. 20-bit resolution. up to 33 V. The AD5790 accepts a positive reference input in the 2. Wide power supply range of up to 16.5 V. range of 5 V to VDD 2.5 V and a negative reference input in the 3. 40C to +125C operating temperature range. range of VSS + 2.5 V to 0 V. The AD5790 offers a relative 4. Low 8 nV/Hz noise. accuracy specification of 2 LSB maximum range, and 5. Low 0.018 ppm/C gain error temperature coefficient. operation is guaranteed monotonic with a 1 LSB to +3 LSB COMPANION PRODUCTS differential nonlinearity (DNL) specification. Output Amplifier Buffer: AD8675, ADA4898-1, ADA4004-1 The part uses a versatile 3-wire serial interface that operates at External Reference: ADR445, ADR4550 clock rates of up to 35 MHz and is compatible with standard serial peripheral interface (SPI), QSPI, MICROWIRE, and DC-to-DC Design Tool: ADIsimPower DSP interface standards. Reference buffers are also provided on Additional companion products on the AD5790 product page. chip. The part incorporates a power-on reset circuit that ensures Table 1. Related Devices the DAC output powers up to 0 V in a known output impedance state and remains in this state until a valid write to the device Part No. Description takes place. The part provides a disable feature that places the AD5791 20-bit, 1 LSB accurate DAC output in a defined load state. The part provides an output AD5780 18-bit, 1 LSB INL, voltage output DAC , buffered reference inputs clamp feature that places the output in a defined load state. AD5781 18-bit, 1 LSB INL, voltage Output DAC , unbuffered reference inputs AD5760 16-bit, 0.5 LSB INL, voltage Output DAC AD5541A/AD5542A 16-bit, 1 LSB accurate 5 V DAC 1 Protected by U.S. Patent No. 7,884,747 and 8,089,380. Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 2011-2018 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 10239-001AD5790 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Serial Interface ............................................................................ 18 Applications ....................................................................................... 1 Standalone Operation ................................................................ 19 Functional Block Diagram .............................................................. 1 Hardware Control Pins .............................................................. 19 General Description ......................................................................... 1 On-Chip Registers ...................................................................... 19 Product Highlights ........................................................................... 1 AD5790 Features ............................................................................ 23 Companion Products ....................................................................... 1 Power-On to 0 V ......................................................................... 23 Revision History ............................................................................... 2 Power-Up Sequence ................................................................... 23 Specifications ..................................................................................... 3 Configuring the AD5790 .......................................................... 23 Timing Characteristics ................................................................ 5 DAC Output State ...................................................................... 23 Absolute Maximum Ratings ............................................................ 7 Output Amplifier Configuration.............................................. 23 ESD Caution .................................................................................. 7 Applications Information .............................................................. 25 Pin Configuration and Function Descriptions ............................. 8 Typical Operating Circuit ......................................................... 25 Typical Performance Characteristics ............................................. 9 Evaluation Board ........................................................................ 26 Terminology .................................................................................... 17 Outline Dimensions ....................................................................... 27 Theory of Operation ...................................................................... 18 Ordering Guide .......................................................................... 27 DAC Architecture ....................................................................... 18 REVISION HISTORY 4/2018Rev. D to Rev. E 2/2012Rev. A to Rev. B Deleted Linearity Compensation Section ................................... 24 Added Power-Up Sequence Section and Figure 50 Renumbered Sequentially ..................................................................................... 23 Updated Outline Dimensions ....................................................... 27 12/2011Rev. 0 to Rev. A Changes to Ordering Guide .......................................................... 27 Changes to Table 1 ............................................................................. 1 Changes to Table 2 ............................................................................. 4 7/2013Rev. C to Rev. D Changes to Figure 48 ...................................................................... 17 Changes to t Test Conditions/Comments and Endnote 2 ......... 5 Changes to DAC Register Section ................................................ 21 1 Deleted Figure 4 ................................................................................ 7 Changes to Table 11 ....................................................................... 22 Updated Outline Dimensions ....................................................... 28 Changes to Pin 11 Description ....................................................... 8 Deleted Daisy-Chain Operation Section ..................................... 19 11/2011Revision 0: Initial Version 7/2012Rev. B to Rev. C Changes to Companion Products Section and to Endnote 1 ..... 1 Changes to Terminology Section.................................................. 18 Changes to Figure 53 ...................................................................... 24 Added Figure 55 .............................................................................. 26 Rev. E Page 2 of 27