Low Cost Low Power Instrumentation Amplifier AD620 FEATURES CONNECTION DIAGRAM Easy to use Gain set with one external resistor 1 8 R R G G (Gain range 1 to 10,000) IN 2 7 +V S Wide power supply range (2.3 V to 18 V) +IN 3 6 OUTPUT Higher performance than 3 op amp IA designs Available in 8-lead DIP and SOIC packaging V 4 5 REF S AD620 Low power, 1.3 mA max supply current TOP VIEW Excellent dc performance (B grade) 50 V max, input offset voltage Figure 1. 8-Lead PDIP (N), CERDIP (Q), and SOIC (R) Packages 0.6 V/C max, input offset drift PRODUCT DESCRIPTION 1.0 nA max, input bias current The AD620 is a low cost, high accuracy instrumentation 100 dB min common-mode rejection ratio (G = 10) amplifier that requires only one external resistor to set gains of Low noise 1 to 10,000. Furthermore, the AD620 features 8-lead SOIC and 9 nV/Hz 1 kHz, input voltage noise DIP packaging that is smaller than discrete designs and offers 0.28 V p-p noise (0.1 Hz to 10 Hz) lower power (only 1.3 mA max supply current), making it a Excellent ac specifications good fit for battery-powered, portable (or remote) applications. 120 kHz bandwidth (G = 100) 15 s settling time to 0.01% The AD620, with its high accuracy of 40 ppm maximum nonlinearity, low offset voltage of 50 V max, and offset drift of 0.6 V/C max, is ideal for use in precision data acquisition APPLICATIONS systems, such as weigh scales and transducer interfaces. Weigh scales Furthermore, the low noise, low input bias current, and low power ECG and medical instrumentation of the AD620 make it well suited for medical applications, such Transducer interface as ECG and noninvasive blood pressure monitors. Data acquisition systems Industrial process controls The low input bias current of 1.0 nA max is made possible with Battery-powered and portable equipment the use of Supereta processing in the input stage. The AD620 works well as a preamplifier due to its low input voltage noise of 9 nV/Hz at 1 kHz, 0.28 V p-p in the 0.1 Hz to 10 Hz band, and 0.1 pA/Hz input current noise. Also, the AD620 is well suited for multiplexed applications with its settling time of 15 s to 0.01%, and its cost is low enough to enable designs with one in-amp per channel. Table 1. Next Generation Upgrades for AD620 30,000 Part Comment 25,000 3 OP AMP IN-AMP AD8221 Better specs at lower price (3 OP-07s) 20,000 AD8222 Dual channel or differential out AD8226 Low power, wide input range 15,000 AD8220 JFET input AD620A AD8228 Best gain accuracy 10,000 R G AD8295 +2 precision op amps or differential out 5,000 AD8429 Ultra low noise 0 0 5 10 15 20 SUPPLY CURRENT (mA) Figure 2. Three Op Amp IA Designs vs. AD620 Rev. H Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 www.analog.com or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.326.8703 20032011 Analog Devices, Inc. All rights reserved. TOTAL ERROR, PPM OF FULL SCALE 00775-0-001 00775-0-002AD620 TABLE OF CONTENTS Specifications .....................................................................................3 RF Interference............................................................................15 Absolute Maximum Ratings ............................................................5 Common-Mode Rejection.........................................................16 ESD Caution ..................................................................................5 Grounding....................................................................................16 Typical Performance Characteristics..............................................6 Ground Returns for Input Bias Currents.................................17 Theory of Operation.......................................................................12 AD620ACHIPS Information.........................................................18 Gain Selection..............................................................................15 Outline Dimensions........................................................................19 Input and Output Offset Voltage ..............................................15 Ordering Guide ...........................................................................20 Reference Terminal .....................................................................15 Input Protection ..........................................................................15 REVISION HISTORY 7/11Rev. G to Rev. H Changes to Input Protection section ............................................15 Deleted Figure 9 ..............................................................................15 Deleted Figure 3.................................................................................1 Changes to RF Interference section..............................................15 Added Table 1 ....................................................................................1 Edit to Ground Returns for Input Bias Currents section...........17 Moved Figure 2..................................................................................1 Added AD620CHIPS to Ordering Guide....................................19 Added ESD Input Diodes to Simplified Schematic ....................12 Changes to Input Protection Section............................................15 Added Figure 41 Renumbered Sequentially ...............................15 7/03Data Sheet Changed from Rev. E to Rev. F Changes to AD620ACHIPS Information Section ......................18 Edit to FEATURES............................................................................1 Updated Ordering Guide ...............................................................20 Changes to SPECIFICATIONS .......................................................2 Removed AD620CHIPS from ORDERING GUIDE ...................4 Removed METALLIZATION PHOTOGRAPH...........................4 12/04Rev. F to Rev. G Replaced TPCs 13 ...........................................................................5 Updated Format.................................................................. Universal Replaced TPC 12...............................................................................6 Change to Features............................................................................1 Replaced TPC 30...............................................................................9 Change to Product Description.......................................................1 Replaced TPCs 31 and 32...............................................................10 Changes to Specifications.................................................................3 Replaced Figure 4............................................................................10 Added Metallization Photograph....................................................4 Changes to Table I...........................................................................11 Replaced Figure 4-Figure 6 ..............................................................6 Changes to Figures 6 and 7 ............................................................12 Replaced Figure 15............................................................................7 Changes to Figure 8 ........................................................................13 Replaced Figure 33..........................................................................10 Edited INPUT PROTECTION section........................................13 Replaced Figure 34 and Figure 35.................................................10 Added new Figure 9........................................................................13 Replaced Figure 37..........................................................................10 Changes to RF INTERFACE section ............................................14 Changes to Table 3 ..........................................................................13 Edit to GROUND RETURNS FOR INPUT BIAS CURRENTS Changes to Figure 41 and Figure 42 .............................................14 section...............................................................................................15 Changes to Figure 43 ......................................................................15 Updated OUTLINE DIMENSIONS.............................................16 Change to Figure 44 ........................................................................17 Rev. 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