Low Cost Instrumentation Amplifier Data Sheet AD622 FEATURES PIN CONFIGURATION Easy to use R 1 8 R G G AD622 Low cost solution IN 2 7 +V S Higher performance than two or three op amp design 3 +IN 6 OUTPUT Unity gain with no external resistor V 4 5 REF S Optional gains with one external resistor Figure 1. 8-Lead PDIP and 8-Lead SOIC N (Gain range: 2 to 1000) (N and R Suffixes) Wide power supply range: 2.6 V to 15 V Available in 8-lead PDIP and 8-lead SOIC N packages GENERAL DESCRIPTION Low power, 1.5 mA maximum supply current The AD622 is a low cost, moderately accurate instrumentation DC performance amplifier in the traditional pin configuration that requires only 0.15% gain accuracy: G = 1 one external resistor to set any gain between 2 and 1000. For a 125 V maximum input offset voltage gain of 1, no external resistor is required. The AD622 is a 1.0 V/C maximum input offset drift complete difference or subtractor amplifier system that also 5 nA maximum input bias current provides superior linearity and common-mode rejection by 66 dB minimum common-mode rejection ratio: G = 1 incorporating precision laser-trimmed resistors. Noise The AD622 replaces low cost, discrete, two or three op amp 12 nV/Hz 1 kHz input voltage noise instrumentation amplifier designs and offers good common- 0.60 V p-p noise: 0.1 Hz to 10 Hz, G = 10 mode rejection, superior linearity, temperature stability, AC characteristics reliability, power, and board area consumption. The low cost of 800 kHz bandwidth: G = 10 the AD622 eliminates the need to design discrete 10 s settling time to 0.1% G = 1 to 100 instrumentation amplifiers to meet stringent cost targets. While 1.2 V/s slew rate providing a lower cost solution, it also provides performance APPLICATIONS and space improvements. Transducer interface Table 1. Next Generation Upgrades for AD622 Low cost thermocouple amplifier Part Comment Industrial process controls Better specs at lower price Difference amplifier AD8221 AD8222 Dual channel or differential out Low cost data acquisition AD8226 Low power, wide input range AD8220 JFET input AD8228 Best gain accuracy AD8295 +2 precision op amps or differential out AD8421 Low noise, better specs Rev. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 19962012 Analog Devices, Inc. All rights reserved. 00777-001AD622 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation .........................................................................9 Applications ....................................................................................... 1 Make vs. Buy: A Typical Application Error Budget ..................9 Pin Configuration ............................................................................. 1 Gain Selection ................................................................................. 11 General Description ......................................................................... 1 Input and Output Offset Voltage .............................................. 11 Revision History ............................................................................... 2 Reference Terminal .................................................................... 11 Specifications ..................................................................................... 3 Input Protection ......................................................................... 11 Absolute Maximum Ratings ............................................................ 5 RF Interference ........................................................................... 12 Thermal Resistance ...................................................................... 5 Ground Returns for Input Bias Currents ................................ 12 ESD Caution .................................................................................. 5 Outline Dimensions ....................................................................... 13 Typical Performance Characteristics ............................................. 6 Ordering Guide .......................................................................... 14 REVISION HISTORY 6/12Rev. D to Rev. E Added Large Input Voltages at Large Gains Section ................. 11 Changes to General Description Section Added Table 1 ........... 1 Replaced RF Interference Section ................................................ 11 Changes to Theory of Operation Section and Figure 16 ............. 9 Deleted Grounding Section .......................................................... 10 Changes to Table 5 .......................................................................... 10 Deleted Figure 16 ............................................................................ 10 Changes to Input Selection Section Deleted Large Input Changes to Ground Returns for Input Bias Currents Section .. 12 Voltages at Large Gains Section Added Figure 18, Renumbered Updated Outline Dimensions ....................................................... 13 Sequentially ..................................................................................... 11 Changes to Ordering Guide .......................................................... 14 Changes to Ordering Guide .......................................................... 14 4/99Rev. B to Rev. C 8/07Rev. C to Rev. D 8/98Rev. A to Rev. B Updated Format .................................................................. Universal Added Thermal Resistance Section ............................................... 5 2/97Rev. 0 to Rev. A Added Figure 16 ................................................................................ 9 1/96Revision 0: Initial Version Rev. E Page 2 of 16