67 MSPS Digital Receive a Signal Processor AD6620 FUNCTIONAL BLOCK DIAGRAM FEATURES High Input Sample Rate 67 MSPS Single Channel Real I II 33.5 MSPS Diversity Channel Real REAL, SERIAL OR CIC FIR DUAL REAL, OUTPUT 33.5 MSPS Single Channel Complex PARALLEL FILTERS FILTER FORMAT OR COMPLEX OUTPUTS Q QQ NCO Frequency Translation INPUTS Worst Spur Better than 100 dBc COS SIN Tuning Resolution Better than 0.02 Hz 2nd Order Cascaded Integrator Comb FIR Filter P EXTERNAL Linear Phase, Fixed Coefficients COMPLEX JTAG OR SERIAL AD6620 SYNC NCO PORT CIRCUITRY CONTROL Programmable Decimation Rates: 2, 3 . . . 16 5th Order Cascaded Integrator Comb FIR Filter Linear Phase, Fixed Coefficients Programmable Decimation Rates: 1, 2, 3 . . . 32 Programmable Decimating RAM Coefficient FIR Filter Up to 134 Million Taps per Second 256 20-Bit Programmable Coefficients Programmable Decimation Rates: 1, 2, 3 . . . 32 both narrowband and wideband carriers to be extracted. The Bidirectional Synchronization Circuitry RAM-based architecture allows easy reconfiguration for multi- Phase Aligns NCOs mode applications. Synchronizes Data Output Clocks The decimating filters remove unwanted signals and noise from Serial or Parallel Baseband Outputs the channel of interest. When the channel of interest occupies Pin Selectable Serial or Parallel less bandwidth than the input signal, this rejection of out-of- Serial Works with SHARC , ADSP-21xx, Most Other band noise is called processing gain. By using large decimation DSPs factors, this processing gain can improve the SNR of the 16-Bit Parallel Port, Interleaved I and Q Outputs ADC by 36 dB or more. In addition, the programmable RAM Two Separate Control and Configuration Ports Coefficient filter allows antialiasing, matched filtering, and Generic P Port, Serial Port static equalization functions to be combined in a single, cost- 3.3 V Optimized CMOS Process effective filter. JTAG Boundary Scan The input port accepts a 16-bit Mantissa, a 3-bit Exponent, and an A/B Select pin. These allow direct interfacing with the GENERAL DESCRIPTION AD6600, AD6640, AD6644, AD9042 and most other high- The AD6620 is a digital receiver with four cascaded signal- speed ADCs. Three input modes are provided: Single Channel processing elements: a frequency translator, two fixed- Real, Single Channel Complex, and Diversity Channel Real. coefficient decimating filters, and a programmable coefficient decimating filter. All inputs are 3.3 V LVCMOS compatible. When paired with an interleaved sampler such as the AD6600, All outputs are LVCMOS and 5 V TTL compatible. the AD6620 can process two data streams in the Diversity Channel Real input mode. Each channel is processed with coher- As ADCs achieve higher sampling rates and dynamic range, it ent frequency translation and output sample clocks. In addition, becomes increasingly attractive to accomplish the final IF stage external synchronization pins are provided to facilitate coherent of a receiver in the digital domain. Digital IF Processing is less frequency translation and output sample clocks among several expensive, easier to manufacture, more accurate, and more AD6620s. These features can ease the design of systems with flexible than a comparable highly selective analog stage. diversity antennas or antenna arrays. The AD6620 diversity channel decimating receiver is designed Units are packaged in an 80-lead PQFP (plastic quad flatpack) to bridge the gap between high-speed ADCs and general pur- and specified to operate over the industrial temperature range pose DSPs. The high resolution NCO allows a single carrier to (40C to +85C). be selected from a high speed data stream. High dynamic range decimation filters with a wide range of decimation rates allow SHARC is a registered trademark of Analog Devices, Inc. REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise Tel: 781/329-4700 www.analog.com under any patent or patent rights of Analog Devices. Fax: 781/326-8703 Analog Devices, Inc., 2001AD6620 TABLE OF CONTENTS ARCHITECTURE As shown in Figure 1, the AD6620 has four main signal pro- GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1 cessing stages: a Frequency Translator, two Cascaded Integrator ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Comb FIR Filters (CIC2, CIC5), and a RAM Coefficient FIR SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Filter (RCF). Multiple modes are supported for clocking data into and out of the chip. Programming and control is accom- TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 plished via serial and microprocessor interfaces. ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . 11 Input data to the chip may be real or complex. If the input data EXPLANATION OF TEST LEVELS . . . . . . . . . . . . . . . . 11 is real, it may be clocked in as a single channel or interleaved with a second channel. The two-channel input mode, called ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Diversity Channel Real, is typically used in diversity receiver PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . 12 applications. Input data is clocked in 16-bit parallel words, PIN CONFIGURATIONS . . . . . . . . . . . . . . . . . . . . . . . . . 13 IN 15:0 . This word may be combined with exponent input bits EXP 2:0 when the AD6620 is being driven by floating-point or INPUT DATA PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 gain-ranging analog-to-digital converters such as the AD6600. OUTPUT DATA PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Frequency translation is accomplished with a 32-bit complex FREQUENCY TRANSLATOR . . . . . . . . . . . . . . . . . . . . . 19 Numerically Controlled Oscillator (NCO). Real data entering SECOND ORDER CASCADED INTEGRATOR this stage is separated into in-phase (I) and quadrature (Q) COMB FILTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 components. This stage translates the input signal from a digital intermediate frequency (IF) to baseband. Phase and amplitude FIFTH ORDER CASCADED INTEGRATOR dither may be enabled on-chip to improve spurious performance COMB FILTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 of the NCO. A phase offset word is available to create a known RAM COEFFICIENT FILTER . . . . . . . . . . . . . . . . . . . . . 25 phase relationship between multiple AD6620s. CONTROL REGISTERS AND ON-CHIP RAM . . . . . . . 27 Following frequency translation is a fixed coefficient, high speed PROGRAMMING THE AD6620 . . . . . . . . . . . . . . . . . . . 30 decimating filter that reduces the sample rate by a program- mable ratio between 2 and 16. This is a second order, cascaded ACCESS PROTOCOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 integrator comb FIR filter shown as CIC2 in Figure 1. (Note: MICROPORT CONTROL . . . . . . . . . . . . . . . . . . . . . . . . 32 Decimation of 1 in CIC2 requires 2 or greater clock into AD6620). The data rate into this stage equals the input data SERIAL PORT CONTROL . . . . . . . . . . . . . . . . . . . . . . . . 35 rate, f . The data rate out of CIC2, f , is determined by SAMP SAMP2 JTAG BOUNDARY SCAN . . . . . . . . . . . . . . . . . . . . . . . . 37 the decimation factor, M . CIC2 APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 44 RCF I-RAM 3 256 18 EXP 2:0 INPUT INTERLEAVE 16 C-RAM DE- DATA M IN 15:0 RCF INTERLEAVE 256 20 CIC5 MULTI- Q-RAM PLEXER 256 18 M SCALING CICS FREQUENCY 3 TRANSLATOR CIC2 MULTI- I 18 PLEXER f SAMP5 23 16 EXP 23 M SCALING CICS 18 SCALING Q OUTPUT f SAMP2 SCALING, S DV OUT OUT COMPLEX I/Q NCO OUT RCF COEFFICIENTS EXPLNV, NUMBER OF TAPS A/B EXPOFF OUT DECIMATE FACTOR MULTIPLEXER CIC2, CIC5 PHASE ADDRESS OFFSET DECIMATE FACTORS OFFSET f SAMP SCALE FACTORS OUTPUT NCO FREQUENCY PARALLEL SERIAL CLK SCALE PHASE OFFSET 16 FACTOR DITHER A/B TIMING SYNC MASK CONTROL REGISTERS RESET OUT 15:0 INPUT MODE MICROPORT AND SCLK REAL, DUAL, COMPLEX FIXED OR WITH EXPONENT SERIAL ACCESS SDI PARALLEL SYNC M/S SDO SYNC NCO 16 OUTPUTS SDFS AND SYNC SYNC CIC SDFE SERIAL I/O I/O JTAG MICROPROCESSOR INTERFACE SBM SYNC RCF WL 1:0 AD TRST TCK TMS TDI TDO D 7:0 A 2:0 CS R/W DS DTACK MODE PAR/SER SDIV 3:0 (W/R) (R/D) (RDY) Figure 1. Block Diagram 2 REV. A