4-Channel, 104 MSPS Digital a Transmit Signal Processor (TSP) AD6623 FEATURES Digital Resampling for Noninteger Interpolation Rates Pin Compatible to the AD6622 NCO Frequency Translation 18-Bit Parallel Digital IF Output Carrier Output from DC to 52 MHz Real or Interleaved Complex Spurious Performance Better than 100 dBc 18-Bit Bidirectional Parallel Digital IF Input/Output Separate 3-Wire Serial Data Input for Each Channel Allows Cascade of Chips for Additional Channels Bidirectional Serial Clocks and Frames Clipped or Wrapped Over Range Microprocessor Control Twos Complement or Offset Binary Output 2.5 V CMOS Core, 3.3 V Outputs, 5 V Inputs Four Independent Digital Transmitters in Single Package JTAG Boundary Scan RAM Coefficient Filter (RCF) APPLICATIONS Programmable IF and Modulation for Each Channel Cellular/PCS Base Stations Programmable Interpolating RAM Coefficient Filter Micro/Pico Cell Base Stations /4-DQPSK Differential Phase Encoder Wireless Local Loop Base Stations 3 /8-PSK Linear Encoder Multicarrier, Multimode Digital Transmit 8-PSK Linear Encoder GSM, EDGE, IS136, PHS, IS95, TDS CDMA, UMTS, Programmable GMSK Look-Up Table CDMA2000 Programmable QPSK Look-Up Table Phased Array Beam Forming Antennas All-Pass Phase Equalizer Software Defined Radio Programmable Fine Scaler Tuning Resolution Better than 0.025 Hz Programmable Power Ramp Unit Real or Complex Outputs High Speed CIC Interpolating Filter FUNCTIONAL BLOCK DIAGRAM NCO = NUMERICALLY CONTROLLED OSCILLATOR/TUNER SDINA I I I I QIN RAM DATA SCALER CHAN A CIC5 rCIC2 SDFIA COEFFICIENT AND SP Q Q Q Q NCO ORT IN FILTER FILTER FILTER POWER 170 SDFOA RAMP SCLKA SDINB I I I I RAM DATA SCALER CHAN B rCIC2 CIC5 COEFFICIENT SDFIB SP Q AND Q Q Q NCO ORT SYNC FILTER FILTER FILTER POWER SDFOB RAMP 4 SCLKB SUMMATION SDINC I I I I RAM SCALER DATA CHAN C CIC5 rCIC2 COEFFICIENT AND SDFIC SP Q Q Q Q NCO ORT FILTER FILTER FILTER POWER SDFOC RAMP SCLKC OEN SDIND I I I I RAM DATA SCALER QOUT CHAN D CIC5 rCIC2 SDFID COEFFICIENT AND SP Q Q Q Q NCO ORT FILTER FILTER FILTER POWER OUT SDFOD RAMP 17:0 SCLKD JTAG MICROPORT TDL TDO TMS TCK TRST D 7:0 DS DTACK RW MODE A 2:0 CS CLK RESET REV. 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No license is granted by implication or otherwise Fax: 781/326-8703 Analog Devices, Inc., 2002 under any patent or patent rights of Analog Devices.AD6623 TABLE OF CONTENTS FEATURES . 1 Start with SoftSync . 30 APPLICATIONS . 1 Start with Pin Sync . 30 FUNCTIONAL BLOCK DIAGRAM . 1 Hop 30 PRODUCT DESCRIPTION 3 Set Frequency No Hop 30 FUNCTIONAL OVERVIEW 3 Hop with SoftSync . 30 RECOMMENDED OPERATING CONDITIONS 4 Hop with Pin Sync . 30 ELECTRICAL CHARACTERISTICS 4 Beam 31 LOGIC INPUTS (5 V TOLERANT) . 4 Set Phase No Beam 31 LOGIC OUTPUTS . 4 Beam with SoftSync 31 IDD SUPPLY CURRENT . 4 Beam with Pin Sync 31 POWER DISSIPATION . 4 Time Slot (Ramp) 31 GENERAL TIMING CHARACTERISTICS . 5 Set Output Power, No Ramp . 31 MICROPROCESSOR PORT TIMING CHARACTERISTICS 6 Time Slot (Ramp) with SoftSync 31 MICROPROCESSOR PORT, MODE INM (MODE = 0) . 6 Time Slot with Pin Sync . 32 MICROPROCESSOR PORT, MOTOROLA (MODE = 1) 6 JTAG INTERFACE 33 TIMING DIAGRAMS . 7 SCALING 33 ABSOLUTE MAXIMUM RATINGS 10 Multicarrier Scaling 33 THERMAL CHARACTERISTICS 10 Single Carrier Scaling . 33 EXPLANATION OF TEST LEVELS 10 MICROPORT INTERFACE . 34 ORDERING GUIDE . 10 Microport Control . 34 PIN CONFIGURATION 128-Lead MQFP 11 EXTERNAL MEMORY MAP 34 128-PIN FUNCTION DESCRIPTION 12 Intel Nonmultiplexed Mode (INM) 35 PIN CONFIGURATION 196-Lead CSPBGA 13 Motorola Nonmultiplexed Mode (MNM) . 35 196-PIN FUNCTION DESCRIPTION 14 External Address 7 Upper Address Register (UAR) 35 POWER SUPPLY . 14 External Address 6 Lower Address Register (LAR) 35 INPUTS . 14 External Address 5 SoftSync 35 CONTROL 14 External Address 4 Sleep 36 MICROPORT CONTROL 14 External Address 3:0 (Data Bytes) . 36 OUTPUTS . 14 INTERNAL CONTROL REGISTERS AND ON-CHIP RAM . 36 JTAG AND BIST 14 AD6623 and AD6622 Compatibility CONTROL REGISTER ADDRESS NOTATION 15 Common Function Registers (not associated with a particular channel) 36 SERIAL DATA PORT 15 Channel Function Registers (0x1xx = Ch. A, Serial Master Mode (SCS = 0) 15 0x2xx = Ch. B, 0x3xx = Ch. C, 0x4xx = Ch. D) 36 Serial Slave Mode (SCS = 1) . 15 (0x000) Summation Mode Control 38 Serial Data Framing 15 (0x001) Sync Mode Control 38 Self-Framing Mode . 15 (0x002) BIST Counter 38 External Framing Mode . 15 (0x003) BIST Result . 38 Serial Port Cascade Configuration . 15 (0xn00) Start Update Hold-Off Counter 39 Serial Data Format . 16 (0xn01) NCO Control 39 PROGRAMMABLE RAM COEFFICIENT FILTER (RCF) . 16 (0xn02) NCO Frequency 39 OVERVIEW OF THE RCF BLOCKS 17 (0xn03) NCO Frequency Update Hold-Off Counter . 39 INTERPOLATING FIR FILTER . 18 (0xn04) NCO Phase Offset . 39 Channel A RCF Control Registers . 20 (0xn05) NCO Phase Offset Update Hold-Off Counter . 39 PSK MODULATOR . 20 (0xn06) CIC Scale . 39 /4-DQSPK Modulation 21 (0xn07) CIC2 Decimation 1 (M 1) . 39 CIC2 8-PSK Modulation . 21 (0xn08) CIC2 Interpolation 1 (L 1) 39 CIC2 3 /8-8-PSK Modulation . 21 (0xn09) CIC5 Interpolation 39 MSK Look-Up Table . 22 (0xn0A) Number of RCF Coefficients 1 . 39 GMSK Look-Up Table . 22 (0xn0B) RCF Coefficient Offset . 39 QPSK Look-Up Table 22 (0xn0C) Channel Mode Control 1 . 39 PHASE EQUALIZER . 22 (0xn0D) Channel Mode Control 2 . 40 FINE SCALE AND RAMP 22 (0xn0E) Fine Scale Factor . 40 FINE SCALING . 22 (0xn0F) RCF Time Slot Sync 40 RCF POWER RAMPING . 22 (0xn100xn11) RCF Phase Equalizer Coefficients . 40 Ramp Triggering . 23 (0xn120xn15) FIR-PSK Magnitudes 40 Special Handling for SYNC0 Pin-Sync . 23 (0xn16) Serial Port Setup 40 CASCADED INTERGRATOR COMB (CIC) (0xn17) Power Ramp Length 0 . 40 INTERPOLATING FILTERS 24 (0xn18) Power Ramp Length 1 . 40 CIC Scaling 24 (0xn19) Power Ramp Rest Time 40 CIC5 24 (0xn200xn1F) Unused . 40 The rCIC2 RESAMPLING INTERPOLATION FILTER 25 (0xn200xn3F) Data Memory 40 Permissible Values of L and M . 25 (0xn400xn17F) Power Ramp Coefficient Memory 40 rCIC2 rCIC2 Frequency Response for rCIC2 . 26 (0xn800xnFF) Coefficient Memory . 40 Programming Guidelines for AD6623 CIC Filters . 26 PSEUDOCODE . 40 NUMERICALLY CONTROLLED OSCILLATOR/TUNER (NCO) . 27 Write Pseudocode 40 Phase Dither 27 Read Pseudocode 41 Amplitude Dither 27 AD6623 EVALUATION PCB AND SOFTWARE 41 Phase Offset 28 APPLICATIONS 42 NCO Frequency Update and Phase Offset Using the AD6623 to Process UMTS Carriers 42 Update Hold-Off Counters . 28 Digital-to-Analog Converter (DAC) Selection 42 NCO Control Scale 28 Multiple TSP Operation . 42 SUMMATION BLOCK . 28 Determining the Number of TSPs to Use . 42 Dual 18-Bit Output Configuration . 28 Programming Multiple TSPs . 43 Output Data Format 28 Driving Multiple TSP Serial Ports . 43 Output Clip Detection 28 USING THE AD6623 TO PROCESS TWO UMTS CARRIERS Cascading Multiple AD6623s . 28 WITH 24 OUTPUT RATE 44 Selection of Real and Complex Data Types 29 Overview . 44 SYNCHRONIZATION . 29 Configuring the AD6623 44 Hold-Off Counters and Shadow Registers . 29 AD6623 Register Configuration . 44 Start 29 THERMAL MANAGEMENT 46 Start with No Sync . 29 OUTLINE DIMENSIONS 47 Revision History . 48 2 REV. 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