QUADRATURE CORRECTION AGC COARSE NCO HALF-BAND FILTER COMPLEX FIR SUM MONITOR SUMMATION VersaCREST Multichannel Digital Upconverter with VersaCREST Crest Reduction Engine AD6633 FEATURES GENERAL DESCRIPTION 4 or 6 wideband digital upconverter channels The AD6633 is a multichannel, wide bandwidth digital VersaCREST crest reduction engine reduces demands on upconverter (DUC) with crest factor reduction (CFR) technology, external power amplifiers which is available in 4-channel or 6-channel versions. It processes One 20-bit complex input port (I, Q interleaved), shared 20-bit baseband input data and generates 18-bit, wideband, real, among 4 or 6 processing channels or complex output data at up to 125 MSPS. This rate is suitable Two 18-bit output ports for parallel I and Q or a single 18-bit for driving digital-to-analog converters (DACs) at the first output port for interleaved I and Q intermediate frequency (IF) directly. All-pass phase equalizer filters (meets IS-95 requirements) Programmable RAM coefficient FIR filters (RCF) with The AD6633 synthesizes multicarrier and multistandard digital resampling signals to drive the DAC(s) with up to six wideband modulated FIR interpolating filters, 2 per channel carriers from a single output port. Each channel includes an Fifth-order interpolating CIC filter, 1 per channel internal peak-to-average power reduction block that reduces Full complex NCO, 32-bit tuning resolution (fine), worst spur power amplifier (PA) power dissipation. The user-configurable better than 105 dBc, 1 per channel interpolating filter (RCF) provides multirate processing Complex FIR filter for frequency equalization or additional (including resampling) and malleable FIR filter characteristics. filtering An all-pass phase equalizer designed to comply with the Output automatic gain control cdma2000 standard follows the RCF. Each channel has its own Full complex composite NCO, 6-bit tuning resolution 32-bit numerically-controlled oscillator (NCO) to up-convert 16-bit/8-bit MicroPort (Intel or Motorola mode) the filtered/interpolated data to the first IF. Interpolation, anti- Serial control port (SPI- or SPORT-compatible) image filtering, all-pass equalization, and NCO tuning functions 3.3 V I/O and 1.8 V core supplies are combined in a single, cost-effective device. JTAG boundary scan User-configurable, built-in, self-test (BIST) capability Digital IF signal processing provides repeatable manufacturing, higher accuracy, and more flexibility than comparable high dynamic range analog designs. The AD6633 uses a 3.3 V I/O APPLICATIONS power supply and a 1.8 V core power supply. Typical power Cellular/PCS basestations consumption is 75 mW per channel or 1.4 W for the complete Micro/pico cell basestations device. All I/O pins are 5 V tolerant. All control registers and Multicarrier cdma2000, WCDMA, TD-SCDMA basestations coefficient values are programmed through a generic 16-bit Broadband wireless access head ends (LMDS, MMDS) microprocessor interface or a SPI/SPORT-compatible serial Software defined radios port. Intel and Motorola microprocessor bus modes are High speed signal processing applications supported. All inputs and outputs are LVCMOS-compatible. For more information about the AD6633, contact Analog Devices via email at versaCOMM analog.com. GAIN 2:0 INPUT CLOCK MULTIPLEXED I AND Q DATA 19:0 I 17:0 MUX I/Q AND FIFO CH 2:0 Q 17:0 VersaCREST WIDEBAND CHANNEL INPUT ACK INPUT REQ Figure 1. Functional Block Diagram Rev. Sp0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 www.analog.com or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.326.8703 2004 Analog Devices, Inc. All rights reserved. 04939-001QUADRATURE CORRECTION AGC COARSE NCO HALF-BAND FILTER COMPLEX FIR SUM MONITOR SUMMATION VersaCREST AD6633 PRODUCT OVERVIEW An all-pass phase equalizer, designed to comply with IS-95, including cdma2000 standards, is the first available block. A The AD6633 is a multichannel, wide bandwidth DUC user-configurable, interpolating RAM coefficient filter (RCF) is with a VersaCREST crest reduction engine. It processes digital baseband input data and generates wideband, real, or complex the first general-purpose filter stage in the channel. It provides IF output data. It drives DACs up to any IF sampled at up to multirate processing, including resampling and malleable finite 125 MSPS. Up to six wideband modulated carriers per package impulse response (FIR) filter characteristics. Further filtering can be achieved from a single output port. Devices may be can be accomplished with two additional, fixed-coefficient, FIR, half-band stages. A fifth-order, cascade integrator comb (CIC5) connected together for additional channels by using multiple is the final filter stage available. packages. Interpolation, anti-image filtering, all-pass equalization, and NCO tuning functions are combined in Each channel has its own 32-bit NCO to upconvert the a single, cost-effective device that includes the VersaCREST filtered/interpolated data to a first IF. crest factor reduction engine. GAIN 3:0 PHASE RESAMPLING FINE FIR1 FIR2 CIC5 EQ RCF NCO VersaCREST REDUCTION ENGINE I 17:0 Figure 2. Wideband Channel Q 17:0 Each VersaCREST wideband channel contains a peak-to- average compensation block that reduces PA requirements. By minimizing infrequent peaks in code-division, multiple- Figure 3. Summation and Post-Sum Blocks access (CDMA) signals, a PA with one-half to one-quarter the previously necessary power capacity can be used. This is done Post-processing after channel summation includes power within standard signal quality requirements and significantly monitoring, filtering, composite NCO, digital automatic gain lowers system cost. control (AGC) output, and quadrature correction stages. The output may be real or complex, and complex output may be The input data is time-multiplexed among the active channels parallel on two 18-bit ports or interleaved on one 18-bit port. for processing through a 20-bit input port. Each channel has a number of elements available to interpolate, resample, and filter Control registers and coefficient values are programmed the data while tuning to an IF for further upconversion within a through a generic 16-bit microprocessor interface or a radio frequency (RF) system. SPI-/SPORT-compatible serial port. Intel and Motorola microprocessor bus modes are supported. The AD6633 uses a 3.3 V I/O power supply and a 1.8 V core power supply. Typical power consumption is 75 mW per channel or 1.4 W for the complete device. All inputs and outputs are LVCMOS-compatible and are 5 V tolerant. 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04939F010/04(Sp0) Rev. Sp0 Page 2 of 2 04939-002 04939-003