80 MSPS, Dual-Channel WCDMA a Receive Signal Processor (RSP) AD6634 FEATURES APPLICATIONS 80 MSPS Wideband Inputs (14 Linear Bits Plus Three Multicarrier, Multimode Digital Receivers RSSI) GSM, IS136, EDGE, PHS, IS95, UMTS, CDMA2000 Processes Two WCDMA Channels (UMTS or CDMA2000 Micro and Pico Cell Systems, Software Radios 1 ) or Four GSM/EDGE, IS136 Channels Wireless Local Loop Four Independent Digital Receivers in a Single Package Smart Antenna Systems Dual 16-Bit Parallel Output Ports In Building Wireless Telephony Dual 8-Bit Link Ports Programmable Digital AGC Loops with 96 dB Range Digital Resampling for Noninteger Decimation Rates Programmable Decimating FIR Filters Interpolating Half-Band Filters Programmable Attenuator Control for Clip Prevention and External Gain Ranging via Level Indicator Flexible Control for Multicarrier and Phased Array 3.3 V I/O, 2.5 V CMOS Core User Configurable Built-In Self-Test (BIST) Capability JTAG Boundary Scan FUNCTIONAL BLOCK DIAGRAM RAM rCIC2 CIC5 PORT A COEFFICIENT RESAMPLER FILTER RCF OUTPUTS LINK PORT CHANNEL 0 OR INA 13:0 CHANNELS 0, 1, 2, 3 PARALLEL EXPA 2:0 NCO PORT IENA INTERPOLATING RAM rCIC2 CIC5 HALF-BAND FILTER COEFFICIENT RESAMPLER PLUS FILTER LIA-A DIGITAL AGC I CHANNEL 1 N LIA-B OUTPUT P NCO MUX U CIRCUITRY T RAM rCIC2 INTERPOLATING CIC5 M COEFFICIENT RESAMPLER HALF-BAND FILTER A FILTER PLUS T DIGITAL AGC INB 13:0 CHANNEL 2 R EXPB 2:0 I PORT B NCO X RCF OUTPUTS LINK PORT IENB OR RAM CHANNELS 0, 1, 2, 3 rCIC2 CIC5 PARALLEL COEFFICIENT RESAMPLER FILTER PORT LIB-A CHANNEL 3 LIB-B NCO BUILT-IN (BIST) MICROPORT OR SERIAL JTAG SYNCA SELF-TEST CIRCUITRY PORT CONTROL EXTERNAL SYNCB SYNC. SYNCC CIRCUIT SYNCD REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties that Tel: 781/329-4700 www.analog.com may result from its use. No license is granted by implication or otherwise Fax: 781/326-8703 Analog Devices, Inc., 2002 under any patent or patent rights of Analog Devices.AD6634 TABLE OF CONTENTS FEATURES . 1 USER CONFIGURABLE BUILT-IN SELF TEST (BIST) 31 APPLICATIONS . 1 RAM BIST . 31 GENERAL DESCRIPTION . 4 Channel BIST . 31 ARCHITECTURE 4 CHIP SYNCHRONIZATION 32 ABSOLUTE MAXIMUM RATINGS . 6 Start . 32 THERMAL CHARACTERISTICS . 6 Start with No Sync 32 EXPLANATION OF TEST LEVELS . 6 Start with Soft Sync . 32 ORDERING GUIDE 6 Start with Pin Sync . 32 RECOMMENDED OPERATING CONDITIONS . 7 Hop . 32 ELECTRICAL CHARACTERISTICS . 7 Set Freq No Hop . 33 GENERAL TIMING CHARACTERISTICS 8 Hop with Soft Sync . 33 MICROPROCESSOR PORT TIMING CHARACTERISTICS 9 Hop with Pin Sync 33 TIMING DIAGRAMS 10 PARALLEL OUTPUT PORTS . 33 PIN CONFIGURATION 17 Channel Mode . 33 PIN FUNCTION DESCRIPTIONS . 18 AGC Mode . 34 EXAMPLE FILTER RESPONSE . 19 Master/Slave PCLK Modes . 35 INPUT DATA PORTS 20 Parallel Port Pin Functionality . 35 Input Data Format 20 LINK PORT 35 Input Timing 20 Link Port Data Format 35 Input Enable Control 20 Link Port Timing . 36 Gain Switching . 21 TigerSHARC Configuration 36 Input Data Scaling 21 MEMORY MAPS 36 Scaling with Fixed-Point ADCs 21 0x000x7F: Coefficient Memory (CMEM) . 36 Scaling with Floating-Point or Gain-Ranging ADCs 22 0x80: Channel Sleep Register 37 NUMERICALLY CONTROLLED OSCILLATOR . 22 0x81: Soft SYNC Register 37 Frequency Translation . 22 0x82: Pin SYNC Register 37 NCO Frequency Hold-Off Register . 23 0x83: Start Hold-Off Counter . 37 Phase Offset . 23 0x84: NCO Frequency Hold-Off Counter 37 NCO Control Register . 23 0x85: NCO Frequency Register 0 37 Bypass . 23 0x86: NCO Frequency Register 1 38 Phase Dither 23 0x87: NCO Phase Offset Register 38 Amplitude Dither . 23 0x88: NCO Control Register 38 Clear Phase Accumulator on HOP 23 0x90: rCIC2 Decimation1 (M 1) 39 rCIC2 Input Enable Control 23 0x91: rCIC2 Interpolation1 (L 1) 39 rCIC2 Mode 00: Blank on IEN Low 23 0x92: rCIC2 Scale 39 Mode 01: Clock on IEN High . 23 0x93: 40 Mode 10: Clock on IEN Transition to High 24 0x94: CIC5 Decimation1 (M 1) . 40 CIC5 Mode 11: Clock on IEN Transition to Low . 24 0x95: CIC5 Scale . 40 WB Input Select 24 0x96: 40 Sync Select 24 0xA0: RCF Decimation1 (M 1) 40 RCF SECOND ORDER rCIC FILTER . 24 0xA1: RCF Decimation Phase (P ) . 40 RCF rCIC2 Rejection 25 0xA2: RCF Number of Taps Minus One (N 1) . 40 RCF Example Calculations 25 0xA3: RCF Coefficient Offset (CO ) 40 RCF Decimation and Interpolation Registers 25 0xA4: RCF Control Register 40 rCIC2 Scale . 25 0xA5: BIST Register for I 40 FIFTH ORDER CIC FILTER 25 0xA6: BIST Register for Q 40 CIC5 Rejection 26 0xA7: BIST Control Register 41 RAM COEFFICIENT FILTER . 27 0xA8: RAM BIST Control Register . 41 RCF Decimation Register 27 0xA9: Output Control Register 41 RCF Decimation Phase 27 Memory Map for Input Port Control Registers 41 RCF Filter Length 27 Input Port Control Registers 41 RCF Output Scale Factor and Control Register 27 0x00 Lower Threshold A . 41 INTERPOLATING HALF-BAND FILTERS 28 0x01 Upper Threshold A . 41 AUTOMATIC GAIN CONTROL . 28 0x02 Dwell Time A . 41 The AGC Loop 29 0x03 Gain Range A Control Register 41 Desired Signal Level Mode . 29 0x04 Lower Threshold B . 42 Desired Clipping Level Mode . 31 0x05 Upper Threshold B . 42 Synchronization 31 0x06 Dwell Time B . 42 0x07 Gain Range B Control Register 42 2 REV. 0