150 MSPS, Wideband, Digital Downconverter (DDC) AD6636 Synchronous serial I/O operation (SPI-, SPORT-compatible) FEATURES Supports 8-bit or 16-bit microport modes 4/6 independent wideband processing channels 3.3 V I/O, 1.8 V CMOS core Processes 6 wideband carriers (UMTS, CDMA2000) User-configurable, built-in, self-test (BIST) capability 4 single-ended or 2 LVDS parallel input ports JTAG boundary scan (16 linear bit plus 3-bit exponent) running at 150 MHz APPLICATIONS Supports 300 MSPS input using external interface logic Three 16-bit parallel output ports operating up to 200 MHz Multicarrier, multimode digital receivers Real or complex input ports GSM, EDGE, PHS, UMTS, WCDMA, CDMA2000, TD-SCDMA, WiMAX Quadrature correction and dc correction for complex inputs Micro and pico cell systems, software radios Supports output rate up to 34 MSPS per channel Broadband data applications RMS/peak power monitoring of input ports Instrumentation and test equipment Programmable attenuator control for external gain ranging Wireless local loops 3 programmable coefficient FIR filters per channel In-building wireless telephony 2 decimating half-band filters per channel 6 programmable digital AGC loops with 96 dB range FUNCTIONAL BLOCK DIAGRAM FIR1 FIR2 MRCF CLKA CIC5 CRCF LHB NCO HB1 HB2 DRCF M = 1-32 M = 1-16 L = Byp, 2 M = Byp, 2 M = Byp, 2 M = 1-16 ADC A/AI EXPA 2:0 FIR1 FIR2 MRCF CIC5 CRCF LHB NCO HB1 HB2 DRCF M = 1-32 M = 1-16 L = Byp, 2 M = Byp, 2 M = Byp, 2 M = 1-16 CLKB PA ADC B/AQ FIR1 FIR2 MRCF CIC5 CRCF LHB EXPB 2:0 NCO HB1 HB2 DRCF M = 1-32 M = 1-16 L = Byp, 2 M = Byp, 2 M = Byp, 2 M = 1-16 CMOS CLKC REAL AGC PB PORTS A, B, ADC C/CI C, D FIR1 FIR2 MRCF CIC5 CRCF LHB NCO HB1 HB2 DRCF M = 1-32 M = 1-16 L = Byp, 2 CMOS M = Byp, 2 M = Byp, 2 M = 1-16 EXPC 2:0 COMPLEX PORTS (AI, AQ) CLKD (BI, BQ) PC FIR1 FIR2 MRCF CIC5 CRCF LHB NCO HB1 HB2 DRCF LVDS ADC D/CQ M = 1-32 M = 1-16 L = Byp, 2 M = Byp, 2 M = Byp, 2 M = 1-16 PORTS AB, CD EXPD 2:0 PEAK/ RMS MEAS. FIR1 FIR2 MRCF RESET CIC5 CRCF LHB NCO HB1 HB2 DRCF I,Q M = 1-32 M = 1-16 L = Byp, 2 M = Byp, 2 M = Byp, 2 M = 1-16 CORR. SYNC 3:0 PRN GEN PLL CLOCK 16-BIT SPORT/SPI INTERFACE JTAG MULTIPLIER MICROPORT INTERFACE NOTE: CHANNELS RENDERED AS ARE AVAILABLE ONLY IN 6-CHANNEL PART M = DECIMATION L = INTERPOLATION Figure 1. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 www.analog.com or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 2005 Analog Devices, Inc. All rights reserved. INPUT MATRIX DATA ROUTER MATRIX PARALLEL PORTS DATA ROUTING 04998-0-001AD6636 TABLE OF CONTENTS General Description ......................................................................... 4 FIR Half-Band Block.................................................................. 30 Specifications..................................................................................... 6 Intermediate Data Router ......................................................... 33 Recommended Operating Conditions ...................................... 6 MonoRate RAM Coefficient Filter (MRCF)........................... 33 Electrical Characteristics............................................................. 6 Decimating RAM Coefficient Filter (DRCF) ......................... 34 , General Timing Characteristics ................................................ 7 Channel RAM Coefficient Filter (CRCF) ............................... 36 , Microport Timing Characteristics ............................................ 8 Interpolating Half-Band Filter.................................................. 38 , , Serial Port Timing Characteristics ........................................... 9 Output Data Router ................................................................... 38 Explanation of Test Levels for Specifications............................ 9 Automatic Gain Control............................................................ 40 Absolute Maximum Ratings.......................................................... 10 Parallel Port Output ................................................................... 44 Thermal Characteristics ............................................................ 10 User-Configurable, Built-In Self-Test (BIST)......................... 48 ESD Caution................................................................................ 10 Chip Synchronization ................................................................ 48 Pin Configuration and Function Descriptions........................... 11 Serial Port Control ..................................................................... 49 Pin Listing for Power, Ground, Data, and Address Buses..... 13 Microport .................................................................................... 58 Timing Diagrams............................................................................ 14 Memory Map .................................................................................. 60 Theory of Operation ...................................................................... 20 Reading the Memory Map Table.............................................. 60 ADC Input Port .......................................................................... 20 Global Register Map .................................................................. 62 PLL Clock Multiplier ................................................................. 21 Input Port Register Map ............................................................ 65 ADC Gain Control..................................................................... 22 Channel Register Map ............................................................... 68 ADC Input Port Monitor Function.......................................... 23 Output Port Register Map......................................................... 73 Quadrature I/Q Correction Block............................................ 25 Design Notes ................................................................................... 77 Input Crossbar Matrix ............................................................... 27 Outline Dimensions ....................................................................... 79 Numerically Controlled Oscillator (NCO) ............................. 27 Ordering Guide .......................................................................... 79 Fifth-Order CIC Filter ............................................................... 29 Rev. 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