Wideband IF Receiver Subsystem Data Sheet AD6676 FEATURES APPLICATIONS High instantaneous dynamic range Wideband cellular infrastructure equipment and repeaters Noise figure (NF) as low as 13 dB Point-to-point microwave equipment Noise spectral density (NSD) as low as 159 dBFS/Hz Instrumentation IIP3 up to 36.9 dBm with spurious tones <99 dBFS Spectrum and communication analyzers Tunable band-pass - analog-to-digital converter (ADC) Software defined radio 20 MHz to 160 MHz signal bandwidth GENERAL DESCRIPTION 70 MHz to 450 MHz IF center frequency 1 The AD6676 is a highly integrated IF subsystem that can Configurable input full-scale level of 2 dBm to 14 dBm digitize radio frequency (RF) bands up to 160 MHz in width Easy to drive resistive IF input centered on an intermediate frequency (IF) of 70 MHz to Gain flatness of 1 dB with under 0.5 dB out-of-band peaking 450 MHz. Unlike traditional Nyquist IF sampling ADCs, the Alias rejection greater than 50 dB AD6676 relies on a tunable band-pass - ADC with a high 2.0 GSPS to 3.2 GSPS ADC clock rate oversampling ratio to eliminate the need for band specific IF On-chip PLL clock multiplier SAW filters and gain stages, resulting in significant simplification of 16-bit I/Q rate up to 266 MSPS the wideband radio receiver architecture. On-chip quadrature On-chip digital signal processing digital downconversion followed by selectable decimation filters NCO and quadrature digital downconverter (QDDC) reduces the complex data rate to a manageable rate between Selectable decimation factor of 12, 16, 24, and 32 62.5 MSPS to 266.7 MSPS. The 16-bit complex output data is Automatic gain control (AGC) support transferred to the host via a single or dual lane JESD204B interface On-chip attenuator with 27 dB span in 1 dB steps supporting line rates of up to 5.333 Gbps. Fast attenuator control via configurable AGC data port Peak detection flags with programmable thresholds Single or dual lane, JESD204B capable Low power consumption: 1.20 W 1.1 V and 2.5 V supply voltage TDD power saving up to 60% 4.3 mm 5.0 mm WLCSP FUNCTIONAL BLOCK DIAGRAM AGC4, AGC3 VSS2IN VSS2OUT VDD2NV AGC2, AGC1 VDDIO RESETB 2.0V CSB REG AGC SCLK SPI SUPPORT 27dB ATTENUATOR SDIO (1dB STEPS) SDO VDDHSI QDDC + VIN+ NCO I I BAND-PASS SERDOUT0+ - ADC Mx VIN SERDOUT0 Q M = 12, Q SERDOUT1+ 16, 24, L+ 32 SERDOUT1 L JESD204B SYNCINB CLOCK CLOCK SUBCLASS 1 SYNTHESIZER GENERATION SYSREF CONTROL AD6676 VDD2 VDDL VDD1 VDDQ VDDC CLK+ CLK VSSA VDDD VSSD Figure 1. 1 This product is protected by U.S. and international patents. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20142017 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. JESD204B SERIALIZER Tx OUTPUTS 12348-001AD6676 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Attenuator.................................................................................... 33 Applications ....................................................................................... 1 Clock Synthesizer ....................................................................... 35 General Description ......................................................................... 1 Digital Processing Blocks .............................................................. 38 Functional Block Diagram .............................................................. 1 Digital Signal Processing Path .................................................. 39 Revision History ............................................................................... 3 AGC Features and Peak Detection ........................................... 42 Product Highlights ........................................................................... 4 GPIO Functionality .................................................................... 44 Specif icat ions ..................................................................................... 5 Power Saving Modes .................................................................. 44 Digital High Speed SERDES Specifications .............................. 7 Introduction to the JESD204B Interface ................................. 45 CLK to SYSREF Timing Diagram ......................................... 8 Functional Overview ................................................................. 47 Digital CMOS Input/Output Specifications ............................. 8 JESD204B Link Establishment ................................................. 47 Absolute Maximum Ratings ............................................................ 9 Physical Layer Input/Outputs ................................................... 49 Thermal Resistance ...................................................................... 9 Configuring the JESD204B Link .............................................. 50 ESD Caution .................................................................................. 9 Synchronization Using SYSREF ............................................. 51 Pin Configuration and Function Descriptions ........................... 10 Applications Information .............................................................. 53 Typical Performance Characteristics ........................................... 12 Analog Input Considerations ................................................... 53 Clock Input Considerations ...................................................... 54 Nominal Performance for IF = 115 MHz (Direct Sampling VHF Receiver) ............................................................................ 12 IF Frequency Planning .............................................................. 56 Nominal Performance for IF = 140 MHz (W Point-to-Point PCB Design Guidelines ............................................................. 57 Receivers) ..................................................................................... 14 Powering the AD6676 ................................................................ 59 Nominal Performance for IF = 181 MHz (Wireless AD6676 Start-Up Initialization ................................................ 61 Infrastructure Receiver)............................................................. 15 Serial Port Interface (SPI) .............................................................. 64 Nominal Performance for IF = 250 MHz AND BW = 75 MHz ....................................................................................................... 17 SPI Register Map Description .................................................. 64 SPI Operation ............................................................................. 64 Nominal Performance for IF = 350 MHz AND BW = 160 MHz ...................................................................................... 19 Register Memory Map and Details .............................................. 66 Equivalent Circuits ......................................................................... 21 Register Memory Map ............................................................... 66 Terminology .................................................................................... 22 Register Details ........................................................................... 68 Theory of Operation ...................................................................... 23 Outline Dimensions ....................................................................... 90 O ver vie w ...................................................................................... 23 Ordering Guide .......................................................................... 90 Band-Pass - ADC Architecture ........................................... 24 - ADC Configuration Considerations ................................ 28 Rev. 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