135 MHz Quad IF Receiver Data Sheet AD6684 FEATURES 4 integrated wideband digital downconverters (DDCs) 48-bit numerically controlled oscillator (NCO), up to JESD204B (Subclass 1) coded serial digital outputs 4 cascaded half-band filters Lane rates up to 15 Gbps 1.4 GHz analog input full power bandwidth 1.68 W total power at 500 MSPS Amplitude detect bits for efficient automatic gain control 420 mW per analog-to-digital converter (ADC) channel (AGC) implementation SFDR = 82 dBFS at 305 MHz (1.8 V p-p input range) Differential clock input SNR = 66.8 dBFS at 305 MHz (1.8 V p-p input range) Integer clock divide by 1, 2, 4, or 8 Noise density = 151.5 dBFS/Hz (1.8 V p-p input range) On-chip temperature diode Analog input buffer Flexible JESD204B lane configurations On-chip dithering to improve small signal linearity Flexible differential input range APPLICATIONS 1.44 V p-p to 2.16 V p-p (1.80 V p-p nominal) Communications 82 dB channel isolation/crosstalk Diversity multiband, multimode digital receivers 0.975 V, 1.8 V, and 2.5 V dc supply operation 3G/4G, W-CDMA, GSM, LTE, LTE-A Noise shaping requantizer (NSR) option for main receiver HFC digital reverse path receivers Variable dynamic range (VDR) option for digital Digital predistortion observation paths predistortion (DPD) General-purpose software radios FUNCTIONAL BLOCK DIAGRAM AVDD2 AVDD1 AVDD1 SR AVDD3 DVDD DRVDD1 DRVDD2 SPIVDD (1.8V) (2.5V) (0.975V) (0.975V) (0.975V) (0.975V) (1.8V) (1.8V) SIGNAL PROCESSING BUFFER 14 VIN+A ADC DIGITAL DOWNCONVERTER CORE VINA (2) 2 VCM AB JESD204B SERDOUTAB0 Tx FD A HIGH SPEED NOISE SHAPED REQUANTIZER OUTPUTS FAST SIGNAL SERIALIZER SERDOUTAB1 (2) DETECT MONITOR FD B BUFFER VARIABLE DYNAMIC RANGE 14 VIN+B (2) ADC CORE VINB SIGNAL MONITOR AND FAST DETECT SYSREF JESD204B CLOCK SUBCLASS 1 SYNCINBAB CLK+ GENERATION CONTROL SYNCINBCD 2 CLK 4 8 SIGNAL PROCESSING BUFFER 14 VIN+C ADC DIGITAL DOWNCONVERTER CORE (2) VINC 2 VCM CD JESD204B SERDOUTCD0 Tx HIGH SPEED FD C NOISE SHAPED REQUANTIZER FAST SIGNAL OUTPUTS SERDOUTCD1 SERIALIZER (2) DETECT MONITOR FD D VARIABLE DYNAMIC RANGE BUFFER 14 VIN+D (2) ADC CORE VIND SPI CONTROL PDWN/STBY AD6684 AGND DRGND SDIO SCLK CSB Figure 1. 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Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 14994-001AD6684 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 DDC Gain Stage ......................................................................... 44 Applications ....................................................................................... 1 DDC Complex to Real Conversion ......................................... 44 Functional Block Diagram .............................................................. 1 DDC Example Configurations ................................................. 45 Revision History ............................................................................... 3 Noise Shaping Requantizer (NSR) ............................................... 49 General Description ......................................................................... 4 Decimating Half-Band Filter .................................................... 49 Product Highlights ........................................................................... 4 NSR Overview ............................................................................ 50 Specif icat ions ..................................................................................... 5 Variable Dynamic Range (VDR) .................................................. 51 DC Specifications ......................................................................... 5 VDR Real Mode .......................................................................... 52 AC Specifications .......................................................................... 6 VDR Complex Mode ................................................................. 52 Digital Specifications ................................................................... 8 Digital Outputs ............................................................................... 54 Switching Specifications .............................................................. 9 Introduction to the JESD204B Interface ................................. 54 Timing Specifications .................................................................. 9 JESD204B Overview .................................................................. 54 Absolute Maximum Ratings .......................................................... 11 Functional Overview ................................................................. 56 Thermal Characteristics ............................................................ 11 JESD204B Link Establishment ................................................. 56 ESD Caution ................................................................................ 11 Physical Layer (Driver) Outputs .............................................. 57 Pin Configuration and Function Descriptions ........................... 12 JESD204B Tx Converter Mapping ........................................... 59 Typical Performance Characteristics ........................................... 14 Setting Up the AD6684 Digital Interface ................................ 60 Equivalent Circuits ......................................................................... 21 Latency ............................................................................................. 64 Theory of Operation ...................................................................... 23 End-To-End Total Latency ........................................................ 64 ADC Architecture ...................................................................... 23 Multichip Synchronization ............................................................ 65 Analog Input Considerations .................................................... 23 SYSREF Setup/Hold Window Monitor ................................. 67 Voltage Reference ....................................................................... 25 Test Modes ....................................................................................... 69 Clock Input Considerations ...................................................... 26 ADC Test Modes ........................................................................ 69 Temperature Diode .................................................................... 27 JESD204B Block Test Modes .................................................... 70 ADC Overrange and Fast Detect .................................................. 28 Serial Port Interface ........................................................................ 72 ADC Overrange .......................................................................... 28 Configuration Using the SPI ..................................................... 72 Fast Threshold Detection (FD A, FD B, FD C and FD D) .... 28 Hardware Interface ..................................................................... 72 Signal Monitor ................................................................................ 29 SPI Accessible Features .............................................................. 72 SPORT Over JESD204B ............................................................. 29 Memory Map .................................................................................. 73 Digital Downconverter (DDC) ..................................................... 32 Reading the Memory Map Register Table ............................... 73 DDC I/Q Input Selection .......................................................... 32 Memory Map .................................................................................. 74 DDC I/Q Output Selection ....................................................... 32 Memory Map Summary ............................................................ 74 DDC General Description ........................................................ 32 Memory Map Details ................................................................. 82 Frequency Translation ................................................................... 38 Applications Information ............................................................ 106 General Description ................................................................... 38 Power Supply Recommendations ........................................... 106 DDC NCO + Mixer Loss and SFDR ........................................ 39 Exposed Pad Thermal Heat Slug Recommendations .......... 106 Numerically Controlled Oscillator ........................................... 39 AVDD1 SR (Pin 64) and AGND SR (Pin 63 and Pin 67) . 106 FIR Filters ........................................................................................ 41 Outline Dimensions ..................................................................... 107 General Description ................................................................... 41 Ordering Guide ........................................................................ 107 Half-Band Filters ........................................................................ 42 Rev. 0 Page 2 of 107