AD7228ABN Analog Devices

2 LC MOS a Octal 8-Bit DAC AD7228A FEATURES FUNCTIONAL BLOCK DIAGRAM Eight 8-Bit DACs with Output Amplifiers Operates with Single +5 V, +12 V or +15 V or Dual Supplies mP Compatible (95 ns WR Pulse) No User Trims Required Skinny 24-Pin DlPs, SOIC, and 28-Terminal Surface Mount Packages GENERAL DESCRIPTION The AD7228A contains eight 8-bit voltage-mode digital-to- analog converters, with output buffer amplifiers and interface PRODUCT HIGHLIGHTS logic on a single monolithic chip. No external trims are required 1. Eight DACs and Amplifiers in Small Package to achieve full specified performance for the part. The single-chip design of eight 8-bit DACs and amplifiers al- Separate on-chip latches are provided for each of the eight D/A lows a dramatic reduction in board space requirements and converters. Data is transferred into the data latches through a offers increased reliability in systems using multiple convert- common 8-bit TTL/CMOS (5 V) compatible input port. Ad- ers. Its pinout is aimed at optimizing board layout with all dress inputs A0, A1 and A2 determine which latch is loaded analog inputs and outputs at one side of the package and all when WR goes low. The control logic is speed compatible with digital inputs at the other. most 8-bit microprocessors. 2. Single or Dual Supply Operation Specified performance is guaranteed for input reference voltages The voltage-mode configuration of the DACs allows single from +2 to +10 V when using dual supplies. The part is also supply operation of the AD7228A. The part can also be oper- specified for single supply +15 V operation using a reference of ated with dual supplies giving enhanced performance for +10 V and single supply +5 V operation using a reference of some parameters. +1.23 V. Each output buffer amplifier is capable of developing 3. Microprocessor Compatibility +10 V across a 2 k load. The AD7228A has a common 8-bit data bus with individual The AD7228A is fabricated on an all ion-implanted, high- DAC latches, providing a versatile control architecture for 2 speed, Linear Compatible CMOS (LC MOS) process which has simple interface to microprocessors. All latch enable signals been specifically developed to integrate high-speed digital logic are level triggered and speed compatible with most high per- circuits and precision analog circuits on the same chip. formance 8-bit microprocessors. REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781/329-4700 Fax: 781/461-3113AD7228ASPECIFICATIONS 1 (V = 10.8 V to 16.5 V V = 5 V 6 10% GND = 0 V V = +2 V to +10 V R = 2 k, C = 100 pF unless otherwise DD SS REF L L noted.) All specifications T to T unless otherwise noted. DUAL SUPPLY MIN MAX BC T U 2 Parameter Version Version Version Version Units Conditions/Comments STATIC PERFORMANCE Resolution 8 8 8 8 Bits 3 Total Unadjusted Error 2 1 2 1 LSB max V = +15 V 10%, V = +10 V DD REF Relative Accuracy 1 1/2 1 1/2 LSB max Differential Nonlinearity 1 1 1 1 LSB max Guaranteed Monotonic 4 Full-Scale Error 1 1/2 1 1/2 LSB max Typical tempco is 5 ppm/C with V = +10 V REF Zero Code Error 25C 25 15 25 15 mV max Typical tempco is 30 V/C T to T 30 20 30 20 mV max MIN MAX Minimum Load Resistance 2 2 2 2 k min V = +10 V OUT REFERENCE INPUT 1 Voltage Range 2 to 10 2 to 10 2 to 10 2 to 10 V min/V max Input Resistance 2 2 2 2 k min 5 Input Capacitance 500 500 500 500 pF max Occurs when each DAC is loaded with all 1s. AC Feedthrough 70 70 70 7 0 dB typ V = 8 V p-p Sine Wave 10 kHz REF DIGITAL INPUTS Input High Voltage, V 2.4 2.4 2.4 2.4 V min INH Input Low Voltage, V 0.8 0.8 0.8 0.8 V max INL Input Leakage Current 1 1 1 1 A max V = 0 V or V IN DD 5 Input Capacitance 8 8 8 8 pF max Input Coding Binary Binary Binary Binary 5 DYNAMIC PERFORMANCE Voltage Output Slew Rate 2 2 2 2 V/s min Voltage Output Settling Time Positive Full-Scale Change 5 5 5 5 s max V = +10 V Settling Time to 1/2 LSB REF Negative Full-Scale Change 5 5 5 5 s max V = +10 V Settling Time to 1/2 LSB REF Digital Feedthrough 50 50 50 50 nV secs typ Code transition all 0s to all 1s. V = 0 V WR = V REF DD 6 Digital Crosstalk 50 50 50 50 nV secs typ Code transition all 0s to all 1s. V = +10 V WR = 0 V REF POWER SUPPLIES V Range 10.8/16.5 10.8/16.5 10.8/16.5 10.8/16.5 V min/V max For Specified Performance DD V Range 4.5/5.5 4.5/5.5 4.5/5.5 4.5/5.5 V min/V max For Specified Performance SS I Outputs Unloaded V = V or V DD IN INL INH 25C 16 16 16 16 mA max T to T 20 20 22 22 mA max MIN MAX I Outputs Unloaded V = V or V SS IN INL INH 25C 14 14 14 14 mA max T to T 18 18 20 20 mA max MIN MAX (V = +15 V 6 10%, V = GND = 0 V V = +10 V, R = 2 k, C = 100 pF unless otherwise noted.) DD SS REF L L SINGLE SUPPLY AII specifications T to T unless otherwise noted. MIN MAX STATIC PERFORMANCE Resolution 8 8 8 8 Bits 3 Total Unadjusted Error 2 1 2 1 LSB max Differential Nonlinearity 1 1 1 1 LSB max Guaranteed Monotonic Minimum Load Resistance 2 2 2 2 k min V = +10 V OUT REFERENCE INPUT Input Resistance 2 2 2 2 k min 5 Input Capacitance 500 500 500 500 pF max Occurs when each DAC is loaded with all 1s. DIGITAL INPUTS As per Dual Supply Specifications 5 DYNAMIC PERFORMANCE Voltage Output Slew Rate 2 2 2 2 V/s min Voltage Output Settling Time Positive Full-Scale Change 5 5 5 5 s max Settling Time to 1/2 LSB Negative Full-Scale Change 7 7 7 7 s max Settling Time to 1/2 LSB Digital Feedthrough 50 50 50 50 nV secs typ Code transition all 0s to all 1s. V = 0 V WR = V REF DD 6 Digital Crosstalk 50 50 50 50 nV secs typ Code transition all 0s to all 1s. V = +10 V, WR = 0 V REF POWER SUPPLIES V Range 13.5/16.5 13.5/16.5 13.5/16.5 13.5/16.5 V min/V max For Specified Performance DD I Outputs Unloaded V = V or V DD IN INL INH 25C 16 16 16 16 mA max T to T 20 20 22 22 mA max MIN MAX NOTES 1 V must be less than V by 3.5 V to ensure correct operation. OUT DD 5 Sample tested at 25C to ensure compliance. 2 Temperature ranges are as follows: 6 The glitch impulse transferred to the output of one converter (not addressed) due to a B, C Versions 40C to +85C change in the digital input code to another addressed converter. T, U Versions 55C to +125C 3 Total Unadjusted Error includes zero code error, relative accuracy and full-scale error. Specifications subject to change without notice. 4 Calculated after zero code error has been adjusted out. B 2 REV.