2
LC MOS
a
12-Bit DACPORTs
AD7245A/AD7248A
FEATURES
AD7245A FUNCTIONAL BLOCK DIAGRAM
12-Bit CMOS DAC with Output Amplifier and
V R
DD OFS
REF OUT
Reference
2R 2R
Improved AD7245/AD7248:
R
FB
12 V to 15 V Operation
1/2 LSB Linearity Grade
V
OUT
Faster Interface30 ns Typ Data Setup Time
V
REF
DAC
Extended Plastic Temperature Range (40C to +85C)
V
SS
AGND
Single or Dual Supply Operation
Low Power65 mW Typ in Single Supply
CS DAC LATCH CLR
Parallel Loading Structure: AD7245A
(8+4) Loading Structure: AD7248A
CONTROL
WR
LOGIC AD7245A
GENERAL DESCRIPTION
LDAC
The AD7245A/AD7248A is an enhanced version of the industry INPUT LATCH
standard AD7245/AD7248. Improvements include operation
from 12 V to 15 V supplies, a 1/2 LSB linearity grade, faster
interface times and better full scale and reference variations with
DB0 DB11 DGND
V . Additional features include extended temperature range
DD
operation for commercial and industrial grades.
AD7248A FUNCTIONAL BLOCK DIAGRAM
The AD7245A/AD7248A is a complete, 12-bit, voltage output,
V R
DD OFS
digital-to-analog converter with output amplifier and Zener voltage REF OUT
reference on a monolithic CMOS chip. No external user trims
2R 2R
R
are required to achieve full specified performance.
FB
Both parts are microprocessor compatible, with high speed data
V
OUT
latches and double-buffered interface logic. The AD7245A accepts
V
REF
DAC
12-bit parallel data that is loaded into the input latch on the
V
SS
AGND
rising edge of CS or WR. The AD7248A has an 8-bit-wide data
bus with data loaded to the input latch in two write operations.
For both parts, an asynchronous LDAC signal transfers data LDAC
DAC LATCH
from the input latch to the DAC latch and updates the analog
WR
CONTROL
AD7248A
output. The AD7245A also has a CLR signal on the DAC latch LOGIC
CSLSB
4-BIT 8-BIT
which allows features such as power-on reset to be implemented.
INPUT INPUT
CSMSB
LATCH LATCH
The on-chip 5 V buried Zener diode provides a low noise, tem-
perature compensated reference for the DAC. For single supply
operation, two output ranges of 0 V to 5 V and 0 V to 10 V are
available, while these two ranges plus an additional 5 V range DB7 DB0 DGND
are available with dual supplies. The output amplifiers are capa-
ble of developing 10 V across a 2 k load to GND.
PRODUCT HIGHLIGHTS
The AD7245A/AD7248A is fabricated in linear compatible CMOS
1. The AD7245A/AD7248A is a 12-bit DACPORT on a single
2
(LC MOS), an advanced, mixed technology process that combines
chip. This single chip design and small package size offer
precision bipolar circuits with low power CMOS logic. The
considerable space saving and increased reliability over
AD7245A is available in a small, 0.3" wide, 24-lead DIP and
multichip designs.
SOIC and in 28-terminal surface mount packages. The AD7248A
2. The improved interface times on the part allows easy, direct
is packaged in a small, 0.3" wide, 20-lead DIP and SOIC and in
interfacing to most modern microprocessors.
20-terminal surface mount packages.
3. The AD7245A/AD7248A features a wide power supply range
allowing operation from 12 V supplies.
DACPORT is a registered trademark of Analog Devices, Inc.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or Tel: 781/329-4700 World Wide Web Site: 1 1
(V = +12 V to +15 V, V = O V or 12 V to 15 V,
AD7245A/AD7248ASPECIFICATIONS
DD SS
AGND = DGND = O V, R = 2 k, C = 100 pF. All specifications T to T unless otherwise noted.)
L L MIN MAX
2 2 2
A B T
Parameter Version Version Version Unit Test Conditions/Comments
STATIC PERFORMANCE
Resolution 12 12 12 Bits
3
Relative Accuracy @ 25C 3/4 1/2 1/2 LSB max
T to T 1 3/4 3/4 LSB max
MIN MAX
T to T 1/2 LSB max V = 15 V 10%
MIN MAX DD
3
Differential Nonlinearity 1 1 1 LSB max Guaranteed Monotonic
3 4
Unipolar Offset Error @ 25C 3 3 3 LSB max V = 0 V or 12 V to 15 V
SS
5
T to T 5 5 5 LSB max Typical Tempco is 3 ppm of FSR /C.
MIN MAX
3 4
Bipolar Zero Error @ 25C 3 2 2 LSB max R connected to REF OUT; V = 12 V to 15 V
OFS SS
5
T to T 5 4 4 LSB max Typical Tempco is 3 ppm of FSR /C.
MIN MAX
3, 6
DAC Gain Error 2 2 2 LSB max
7
Full-Scale Output Voltage Error @ 25C 0.2 0.2 0.2 % of FSR max V = 15 V
DD
4
Full Scale/ V 0.06 0.06 0.06 % of FSR/V max V = +12 V to +15 V
DD DD
4
Full Scale/ V 0.01 0.01 0.01 % of FSR/V max V = 12 V to 15 V
SS SS
8
Full-Scale Temperature Coefficient 40 30 40 ppm of FSR/C max V = 15 V
DD
REFERENCE OUTPUT
REF OUT @ 25C 4.99/5.01 4.99/5.01 4.99/5.01 V min/V max V = 15 V
DD
4
REF OUT/ V 2 2 2 mV/V max V = 12 V to 15 V
DD DD
Reference Temperature Coefficient 25 25 35 ppm/C typ
Reference Load Change
( REF OUT vs. I) 1 1 1 mV max Reference Load Current Change (0100 A)
DIGITAL INPUTS
Input High Voltage, V 2.4 2.4 2.4 V min
INH
Input Low Voltage, V 0.8 0.8 0.8 V max
INL
Input Current, I 10 10 10 A max V = 0 V to V
IN IN DD
9
Input Capacitance 8 8 8 pF max
ANALOG OUTPUTS
Output Range Resistors 15/30 15/30 15/30 k min/k max
10
Output Voltage Ranges 5, 10 5, 10 5, 10 V V = 0 V; Pin Strappable
SS
4
5, 10, 5, 10, 5, 10, V = 12 V to 15 V; Pin Strappable
SS
5 5 5V
DC Output Impedance 0.5 0.5 0.5 typ
9
AC CHARACTERISTICS
Voltage Output Settling Time Settling Time to Within 1/2 LSB of Final Value
Positive Full-Scale Change 7 7 10 s max DAC Latch All 0s to All 1s
4
Negative Full-Scale Change 7 7 10 s max DAC Latch All 1s to All 0s; V = 12 V to 15 V
SS
Output Voltage Slew Rate 2 2 1.5 V/ s min
3
Digital Feedthrough 10 10 10 nV-s typ
Digital-to-Analog Glitch Impulse 30 30 30 nV-s typ
POWER REQUIREMENTS
V +10.8/ +10.8/ +10.8/ V min/ For Specified Performance Unless Otherwise Stated
DD
+16.5 +16.5 +16.5 V max
V 10.8/ 10.8/ 10.8/ V min/ For Specified Performance Unless Otherwise Stated
SS
16.5 16.5 16.5 V max
I @ 25C 9 9 9 mA max Output Unloaded; Typically 5 mA
DD
T to T 10 10 12 mA max Output Unloaded
MlN MAX
I (Dual Supplies) 3 3 5 mA max Output Unloaded; Typically 2 mA
SS
NOTES
1
Power supply tolerance is 10%.
2
Temperature ranges are as follows: A/B Versions; 40C to +85C; T Version; 55C to +125C.
3
See Terminology.
4
With appropriate power supply tolerances.
5
FSR means Full-Scale Range and is 5 V for the 0 V to 5 V output range and 10 V for both the 0 V to 10 V and 5 V output ranges.
6
This error is calculated with respect to the reference voltage and is measured after the offset error has been allowed for.
7
This error is calculated with respect to an ideal 4.9988 V on the 0 V to 5 V and 5 V ranges; it is calculated with respect to an ideal 9.9976 V on the 0 V to 10 V
range. It includes the effects of internal voltage reference, gain and offset errors.
8
Full-Scale TC = FS/ T, where FS is the full-scale change from T = 25C to T or T .
A MIN MAX
9
Guaranteed by design and characterization, not production tested.
10
0 V to 10 V output range is available only when V +14.25 V.
DD
Specifications subject to change without notice.
2
REV. B