2 LC MOS a Dual 12-Bit Serial DACPORT AD7249 FEATURES FUNCTIONAL BLOCK DIAGRAM Two 12-Bit CMOS DAC Channels with On-Chip Voltage Reference V V DD SS Output Amplifiers Three Selectable Output Ranges per Channel 2R AD7249 R OFSA 5 V to +5 V, 0 V to +5 V, 0 V to +10 V REFOUT 2R Serial Interface 125 kHz DAC Update Rate A1 V Small Size: 16-Lead DIP or SOIC OUTA 12-BIT DAC A Low Power Dissipation REFIN 2R R OFSB APPLICATIONS 2R Process Control AGND Industrial Automation V A2 OUTB Digital Signal Processing Systems 12-BIT DAC B Input/Output Ports DGND INPUT SHIFT REGISTER GENERAL DESCRIPTION The AD7249 DACPORT contains a pair of 12-bit, voltage- SCLK SDIN SYNC BIN/COMP CLR LDAC output, digital-to-analog converters with output amplifiers and Zener voltage reference on a monolithic CMOS chip. No exter- nal trims are required to achieve full specified performance. The AD7249 features a serial interface which allows easy con- nection to both microcomputers and 16-bit digital signal proces- The output amplifiers are capable of developing +10 V across a sors with serial ports. The serial data may be applied at rates up 2 k load. The output voltage ranges with single supply opera- to 2 MHz allowing a DAC update rate of 125 kHz. tion are 0 V to +5 V or 0 V to +10 V, while an additional bipolar 5 V output range is available with dual supplies. The ranges The AD7249 is fabricated on linear compatible CMOS 2 are selected using the internal gain resistor. (LC MOS), an advanced, mixed technology process. It is pack- aged in 16-lead DIP and 16-lead SOIC packages. Interfacing to the AD7249 is serial, minimizing pin count and allowing a small package size. Standard control signals allow PRODUCT HIGHLIGHTS interfacing to most DSP processors and microcontrollers. The 1. Two complete 12-bit DACPORTs data stream consists of 16 bits, DB15 to DB13 are dont care The AD7249 contains two complete voltage output, 12-bit bits, the 13th bit (DB12) is used as the channel select bit and DACs in both 16-lead DIP and SOIC packages. the remaining 12 bits (DB11 to DB0) contain the data to update the DAC. The 16-bit data word is clocked into the input register 2. Single or dual supply operation on each falling SCLK edge. 3. Minimum 3-wire interface to most DSP processors The data format is natural binary in both unipolar ranges, while 4. DAC update rate125 kHz either offset binary or twos complement format may be selected in the bipolar range. A CLR function is provided which sets the output to 0 V in both unipolar ranges and in the twos comple- ment bipolar range, while with offset binary data format, the output is set to REFIN. This function is useful as a power-on reset as it allows the outputs to be set to a known voltage level. DACPORT is a registered trademark of Analog Devices, Inc. REV. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties Tel: 781/329-4700 World Wide Web Site: 1 1 (V = +12 V to +15 V, V = O V or 12 V to 15 V, AGND = DGND = O V, REFIN = AD7249SPECIFICATIONS DD SS +5 V, R = 2 k , C = 100 pF to AGND. All specifications T to T unless otherwise noted.) L L MIN MAX 2 2 2 Parameter A Version B Version S Version Unit Test Conditions/Comments STATIC PERFORMANCE Resolution 12 12 12 Bits 3 Relative Accuracy 1 1/2 1 LSB max 3 Differential Nonlinearity 0.9 0.9 0.9 LSB max Guaranteed Monotonic 3 1 Unipolar Offset Error 5 5 6 LSB max V = 0 V or 12 V to 15 V DAC SS Latch Contents All 0s 3 1 Bipolar Zero Error 6 5 7 LSB max V = 12 V to 15 V SS DAC Latch Contents All 0s 3, 4 Full-Scale Error 6 6 7 LSB max Full-Scale Temperature Coefficient 5 5 5 ppm of FSR/C typ REFERENCE OUTPUT REFOUT 4.95/5.05 4.95/5.05 4.95/5.05 V min/V max Reference Temperature Coefficient 25 25 30 ppm/C typ Reference Load Change ( V vs. I ) 1 1 1 mV max Reference Load Current (I ) REFOUT L L Change (0 A100 A) REFERENCE INPUT Reference Input Range, REFIN 4.95/5.05 4.95/5.05 4.95/5.05 V min/V max 5 V 1% Input Current 5 5 5 A max DIGITAL INPUTS Input High Voltage, V 2.4 2.4 2.4 V min INH Input Low Voltage, V 0.8 0.8 0.8 V max INL Input Current I 1 1 1 A max V = 0 V to V IN IN DD 5 Input Capacitance 8 8 8 pF max ANALOG OUTPUTS Output Range Resistor, R & R 15/30 15/30 15/30 k min/ max OFSA OFSB 6 Output Voltage Ranges +5, +10 +5, +10 +5, +10 V Single Supply V = 0 V SS 6 Output Voltage Ranges +5, +10, 5 +5, +10, 5 +5, +10, 5 V Dual Supply V = 12 V or 15 V SS DC Output Impedance 0.5 0.5 0.5 typ 5 AC CHARACTERISTICS Voltage Output Settling-Time Settling Time to Within 1/2 LSB of Final Value Positive Full-Scale Change 10 10 10 s max Typically 3 s Negative Full-Scale Change 10 10 10 s max Typically 5 s 3 Digital-to-Analog Glitch Impulse 30 30 30 nV secs typ 1 LSB Change Around Major Carry 3 Digital Feedthrough 10 10 10 nV secs typ 3 Digital Crosstalk 10 10 10 nV secs typ POWER REQUIREMENTS V Range +10.8/+16.5 +11.4/+15.75 +11.4/+15.75 V min/V max For Specified Performance Unless DD Otherwise Stated Range (Dual Supplies) 10.8/16.5 11.4/15.75 11.4/15.75 V min/V max For Specified Performance Unless V SS Otherwise Stated I 15 15 15 mA max Output Unloaded Typically 11 mA DD I (Dual Supplies) 5 5 5 mA max Output Unloaded Typically 3 mA SS NOTES 1 Power supply tolerance, A Version: 10% B, S Versions: 5%. 2 Temperature ranges are as follows: A, B Versions: 40C to +85C S Version: 55C to +125C. 3 See Terminology. 4 Measured with respect to REFIN and includes unipolar/bipolar offset error. 5 Guaranteed by design not production tested. 6 0 V to 10 V output range available only with V 14.25 V. DD Specifications subject to change without notice. 2 REV. D