Low Cost, Low Power CMOS General-Purpose Dual Analog Front End AD73322L FEATURES FUNCTIONAL BLOCK DIAGRAM Two 16-bit A/D converters AVDD1 AVDD2 DVDD Two 16-bit D/A converters AD73322L Programmable input/output sample rates VFBP1 VINP1 SDI ADC CHANNEL 1 78 dB ADC SNR VINN1 SDIFS VFBN1 78 dB DAC SNR 64 kHz maximum sample rate VOUTP1 DAC CHANNEL 1 SCLK VOUTN1 90 dB crosstalk Low group delay (25 s typ per ADC channel, 50 s typ per REFOUT SE REFERENCE SPORT DAC channel) REFCAP RESET Programmable input/output gain VFBP2 VINP2 ADC CHANNEL 2 MCLK Flexible serial port allows up to 4 dual codecs to be VINN2 connected in cascade, giving 8 I/O channels VFBN2 Single-supply operation (2.7 V to 3.3 V) VOUTP2 SDOFS DAC CHANNEL 2 50 mW typ power consumption at 3.0 V VOUTN2 SDO Temperature range: 40C to +105C On-chip reference AGND1 AGND2 DGND 28-lead SOIC, TSSOP, and 44-lead LQFP packages Figure 1. APPLICATIONS General-purpose analog I/O Speech processing Cordless and personal communications Telephony Active control of sound and vibration Data communications Wireless local loop GENERAL DESCRIPTION The A/D and D/A conversion channels feature programmable The AD73322L is a dual front-end processor for general- purpose applications, including speech and telephony. It input/output gains with ranges of 38 dB and 21 dB, respectively. features two 16-bit A/D conversion channels and two 16-bit An on-chip reference voltage allows single-supply operation. D/A conversion channels. Each channel provides 78 dB signal- The sampling rate of the codecs is programmable with four to-noise ratio over a voice-band signal bandwidth. It also separate settings offering 64 kHz, 32 kHz, 16 kHz, and 8 kHz features an input-to-output gain network in both the analog sampling rates (from a master clock of 16.384 MHz). and digital domains. This is featured on both codecs and can be used for impedance matching or scaling when interfacing to A serial port (SPORT) allows easy interfacing of single or subscriber line interface circuits (SLICs). cascaded devices to industry-standard DSP engines. The SPORT transfer rate is programmable to allow interfacing to The AD73322L is particularly suitable for a variety of appli- both fast and slow DSP engines. cations in the speech and telephony area, including low bit rate, high quality compression, speech enhancement, recognition, The AD73322L is available in 28-lead SOIC, 28-lead TSSOP, and synthesis. The low group delay characteristic of the part and 44-lead LQFP packages. makes it suitable for single or multichannel active control applications. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 www.analog.com or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.326.8703 2004 Analog Devices, Inc. All rights reserved. 00691-001AD73322L TABLE OF CONTENTS Specifications..................................................................................... 4 Sample Rate Divider................................................................... 19 Current Summary......................................................................... 6 DAC Advance Register .............................................................. 20 Signal Ranges ................................................................................ 7 Control Register A ..................................................................... 21 Timing Characteristics ................................................................ 7 Control Register B...................................................................... 21 Timing Diagrams.......................................................................... 8 Control Register C...................................................................... 21 Absolute Maximum Ratings............................................................ 9 Control Register D ..................................................................... 22 ESD Caution.................................................................................. 9 Control Register E...................................................................... 22 Pin Configurations and Function Descriptions ......................... 10 Control Register F ...................................................................... 22 Terminology .................................................................................... 12 Control Register G ..................................................................... 23 Abbreviations .............................................................................. 12 Control Register H ..................................................................... 23 Typical Performance Characteristics and Functional Block Operation......................................................................................... 24 Diagram ........................................................................................... 13 Resetting the AD73322L ........................................................... 24 Functional Descriptions ................................................................ 14 Power Management ................................................................... 24 Encoder Channels ...................................................................... 14 Operating Modes........................................................................ 24 Programmable Gain Amplifier................................................. 14 Program (Control) Mode.......................................................... 24 ADC ............................................................................................. 14 Data Mode................................................................................... 25 Analog Sigma-Delta Modulator ............................................... 14 Mixed Program/Data Mode...................................................... 25 Decimation Filter........................................................................ 15 Digital Loop-Back Mode........................................................... 25 ADC Coding ............................................................................... 15 SPORT Loop-Back Mode.......................................................... 25 Decoder Channel........................................................................ 16 Analog Loop-Back Mode .......................................................... 26 DAC Coding................................................................................ 16 Interfacing ....................................................................................... 27 Interpolation Filter ..................................................................... 16 Cascade Operation..................................................................... 27 Analog Smoothing Filter and PGA.......................................... 16 Performance .................................................................................... 29 Differential Output Amplifiers................................................. 16 Encoder Section.......................................................................... 29 Voltage Reference ....................................................................... 16 Encoder Group Delay ................................................................ 30 Analog and Digital Gain Taps................................................... 17 Decoder Section ......................................................................... 30 Digital Gain Tap.......................................................................... 18 On-Chip Filtering....................................................................... 31 Serial Port (SPORT) ................................................................... 18 Decoder Group Delay................................................................ 31 SPORT Overview........................................................................ 18 Design Considerations................................................................... 32 SPORT Register Maps................................................................ 19 Analog Inputs ............................................................................. 32 Master Clock Divider................................................................. 19 Interfacing to an Electret Microphone .................................... 34 Serial Clock Rate Divider .......................................................... 19 Rev. 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