Six-Input Channel a Analog Front End AD73360L FEATURES metering or multichannel analog inputs. It features six 16-bit Six 16-Bit A/D Converters A/D conversion channels, each of which provides 76 dB signal- Programmable Input Sample Rate to-noise ratio over a dc-to-4 kHz signal bandwidth. Each Simultaneous Sampling channel also features a programmable input gain amplifier (PGA) 76 dB SNR with gain settings in eight stages from 0 dB to 38 dB. 64 kS/s Maximum Sample Rate The AD73360L is particularly suitable for industrial power 95 dB Crosstalk metering as each channel samples synchronously, ensuring that Low Group Delay (25 s Typ per ADC Channel) there is no (phase) delay between the conversions. The AD73360L Programmable Input Gain also features low group delay conversions on all channels. Flexible Serial Port Which Allows Multiple Devices to An on-chip reference voltage is included with a nominal value Be Connected in Cascade of 1.2 V. Single (2.7 V to 3.6 V) Supply Operation 80 mW Max Power Consumption at 2.7 V The sampling rate of the device is programmable, with four On-Chip Reference separate settings offering 64 kHz, 32 kHz, 16 kHz, and 8 kHz 28-Lead SOIC Package sampling rates (from a master clock of 16.384 MHz). APPLICATIONS A serial port (SPORT) allows easy interfacing of single or cas- General-Purpose Analog Input caded devices to industry-standard DSP engines. The SPORT Industrial Power Metering transfer rate is programmable to allow interfacing to both fast Motor Control and slow DSP engines. Simultaneous Sampling Applications The AD73360L is available in 28-lead SOIC package. GENERAL DESCRIPTION The AD73360L is a six-input channel analog front-end proces- sor for general-purpose applications, including industrial power FUNCTIONAL BLOCK DIAGRAM VINP1 ANALOG SIGNAL 0/38dB - DECIMATOR SDI CONDITIONING PGA MODULATOR VINN1 SDIFS VINP2 SCLK ANALOG SIGNAL 0/38dB - DECIMATOR CONDITIONING PGA MODULATOR VINN2 VINP3 ANALOG SIGNAL 0/38dB - DECIMATOR CONDITIONING PGA MODULATOR VINN3 RESET REFERENCE REFCAP SERIAL AD73360L I/O MCLK REFOUT PORT SE VINP4 ANALOG SIGNAL 0/38dB - DECIMATOR CONDITIONING PGA MODULATOR VINN4 VINP5 ANALOG SIGNAL 0/38dB - DECIMATOR CONDITIONING PGA MODULATOR SDO VINN5 SDOFS VINP6 ANALOG SIGNAL 0/38dB - DECIMATOR CONDITIONING PGA MODULATOR VINN6 REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or Tel: 781/329-4700 World Wide Web Site: (AVDD = 2.7 V to 3.6 V DVDD = 2.7 V to 3.6 V DGND = AGND = 0 V, f = 16.384 MHz, MCLK 1 AD73360LSPECIFICATIONS f = 8.192 MHz, f = 8 kHz T = T to T , unless otherwise noted.) SCLK S A MIN MAX AD73360LA Parameter Min Typ Max Unit Test Conditions/Comments REFERENCE REFCAP Absolute Voltage, V 1.08 1.2 1.32 V REFCAP REFCAP TC 50 ppm/C 0.1 F Capacitor Required from REFCAP to AGND2 REFOUT Typical Output Impedance 130 Absolute Voltage, V 1.08 1.2 1.32 V Unloaded REFOUT Minimum Load Resistance 1 k Maximum Load Capacitance 100 pF ADC SPECIFICATIONS 2, 3 Maximum Input Range at VIN 1.578 V p-p Measured Differentially 2.85 dBm Nominal Reference Level at VIN 1.0954 V p-p Measured Differentially (0 dBm0) 6.02 dBm Absolute Gain PGA = 0 dB 1.3 +0.6 dB 1.0 kHz PGA = 38 dB 0.6 dB 1.0 kHz Signal to (Noise + Distortion) PGA = 0 dB 76 dB 0 Hz to 4 kHz f = 8 kHz S PGA = 0 dB 71 76 dB 0 Hz to 2 kHz f = 8 kHz f = 60 Hz S IN PGA = 38 dB 58 dB 0 Hz to 4 kHz f = 64 kHz S Total Harmonic Distortion PGA = 0 dB 80 71 dB 0 Hz to 2 kHz f = 8 kHz f = 60 Hz S IN PGA = 38 dB 64 dB 0 Hz to 2 kHz f = 64 kHz f = 60 Hz S IN Intermodulation Distortion 78 dB PGA = 0 dB Idle Channel Noise 68 dB PGA = 0 dB, f = 64 kHz S = 16 MHz S CLK Crosstalk ADC-to-ADC 95 dB ADC1 at Idle ADC2 to ADC6 Input Signal: 60 Hz DC Offset 30 +30 mV PGA = 0 dB Power Supply Rejection 55 dB Input Signal Level at AVDD and DVDD Pins 1.0 kHz, 100 mV p-p Sine Wave 4, 5 Group Delay 25 s 64 kHz Output Sample Rate 50 s 32 kHz Output Sample Rate 95 s 16 kHz Output Sample Rate 190 s 8 kHz Output Sample Rate 2, 4 6 Input Resistance at VIN 25 k DMCLK = 16.384 MHz Phase Mismatch 0.15 Degrees f = 1 kHz IN 0.01 Degrees f = 60 Hz IN FREQUENCY RESPONSE 7 (ADC) Typical Output Frequency (Normalized to f ) S 00dB 0.03125 0.1 dB 0.0625 0.25 dB 0.125 0.6 dB 0.1875 1.4 dB 0.25 2.8 dB 0.3125 4.5 dB 0.375 7.0 dB 0.4375 9.5 dB > 0.5 < 12.5 dB LOGIC INPUTS V , Input High Voltage V 0.8 V V INH DD DD V , Input Low Voltage 0 0.8 V INL I , Input Current 10 A IH C , Input Capacitance 10 pF IN 2 REV. 0