3 V Serial-Input a Micropower 10-Bit and 12-Bit DACs AD7390/AD7391 FEATURES FUNCTIONAL BLOCK DIAGRAM Micropower100 A Single-Supply2.7 V to 5.5 V Operation V AD7390 DD Compact 1.75 mm Height SO-8 Package REF V 12-BIT DAC OUT and 1.1 mm Height TSSOP-8 Package 12 AD739012-Bit Resolution CLR GND AD739110-Bit Resolution DAC REGISTER LD SPI and QSPI Serial Interface Compatible with Schmitt EN 12 Trigger Inputs CLK SERIAL REGISTER SDI APPLICATIONS Automotive 0.5 V to 4.5 V Output Span Voltage Portable Communications Digitally Controlled Calibration GENERAL DESCRIPTION in (SDI), clock (CLK) and load strobe (LD) pins. Addition- The AD7390/AD7391 family of 10-bit and 12-bit voltage- ally, a CLR input sets the output to zero scale at power on or output digital-to-analog converters is designed to operate upon user demand. from a single 3 V supply. Built using a CBCMOS process, Both parts are offered in the same pinout to allow users to select these monolithic DACs offer the user low cost, and ease-of-use the amount of resolution appropriate for their application without in single-supply 3 V systems. Operation is guaranteed over the circuit card redesign. supply voltage range of 2.7 V to 5.5 V consuming less than 100 A The AD7390/AD7391 are specified over the extended industrial making this device ideal for battery operated applications. ( 40C to 85C) temperature range. The AD7391AR is The full-scale voltage output is determined by the external specified for the 40C to 125C automotive temperature reference input voltage applied. The rail-to-rail REF to IN range. The AD7390/AD7391s are available in plastic DIP, and DAC allows for a full-scale voltage set equal to the positive OUT low profile 1.75 mm height SO-8 surface mount packages. The supply V or any value in between. DD AD7391ARU is available for ultracompact applications in a thin A doubled-buffered serial-data interface offers high-speed, 1.1 mm TSSOP-8 package. 3-wire, SPI and microcontroller compatible inputs using data 1.00 2.0 AD7390 AD7390 0.75 1.5 +25 C, +85 C 0.50 1.0 0.25 0.5 0.00 0.0 0.25 0.5 55 C 0.50 1.0 V = 3.0V DD V = 3.0V DD T = 55 C, +25 C, +85 C 0.75 1.5 A V = 2.5V REF SUPERIMPOSED 1.00 2.0 0 512 1024 1536 2048 2560 3072 3584 4096 0 512 1024 1536 2048 2560 3072 2584 4096 CODE Decimal CODE Decimal Figure 1. Differential Nonlinearity Error vs. Code Figure 2. INL Error vs. Code and Temperature REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties that Tel: 781/329-4700 www.analog.com may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 Analog Devices, Inc., 2002 DNL LSB INL LSBAD7390/AD7391SPECIFICATIONS ( V = 2.5 V, 40 C < T < +85 C unless otherwise noted.) AD7390 ELECTRICAL CHARACTERISTICS REF IN A Parameter Symbol Conditions 3 V 10% 5 V 10% Unit STATIC PERFORMANCE 1 Resolution N 12 12 Bits 2 Relative Accuracy INL T = 25C 1.6 1.6 LSB max A INL T = 40C, 85C 2.0 2 LSB max A 2 Differential Nonlinearity DNL T = 25C, Monotonic 0.9 0.9 LSB max A DNL Monotonic 1 1 LSB max Zero-Scale Error V Data = 000 4.0 4.0 mV max ZSE H Full-Scale Voltage Error V T = 25C, 85C, Data = FFF 8 8mV max FSE A H V T = 40C, Data = FFF 20 20 mV max FSE A H 3 Full-Scale Tempco TCV 16 16 ppm/C typ FS REFERENCE INPUT V Range V 0/V 0/V V min/max REF IN REF DD DD 4 Input Resistance R 2.5 2.5 M typ REF 3 Input Capacitance C 5 5 pF typ REF ANALOG OUTPUT Output Current (Source) I Data = 800 , V = 5 LSB 1 1 mA typ OUT H OUT Output Current (Sink) I Data = 800 , V = 5 LSB 3 3 mA typ OUT H OUT 3 Capacitive Load C No Oscillation 100 100 pF typ L LOGIC INPUTS Logic Input Low Voltage V 0.5 0.8 V max IL Logic Input High Voltage V V 0.6 V 0.6 V min IH DD DD Input Leakage Current I 10 10 A max IL 3 Input Capacitance C 10 10 pF max IL 3, 5 INTERFACE TIMING Clock Width High t 50 30 ns min CH Clock Width Low t 50 30 ns min CL Load Pulsewidth t 30 20 ns min LDW Data Setup t 10 10 ns min DS Data Hold t 30 15 ns min DH Clear Pulsewidth t 15 15 ns min CLRW Load Setup t 30 15 ns min LD1 Load Hold t 40 20 ns min LD2 6 AC CHARACTERISTICS Output Slew Rate SR Data = 000 to FFF to 000 0.05 0.05 V/ s typ H H H Settling Time t To 0.1% of Full Scale 70 60 s typ S DAC Glitch Q Code 7FF to 800 to 7FF 65 65 nVs typ H H H Digital Feedthrough Q 15 15 nVs typ Feedthrough V /V V = 1.5 V 1 V p-p 63 63 dB typ OUT REF REF DC , Data = 000 , f = 100 kHz H SUPPLY CHARACTERISTICS Power Supply Range V DNL < 1 LSB 2.7/5.5 2.7/5.5 V min/max DD RANGE Positive Supply Current I V = 0 V, No Load, T = 25C55 55 A typ DD IL A I V = 0 V, No Load 100 100 A max DD IL Power Dissipation P V = 0 V, No Load 300 500 W max DISS IL Power Supply Sensitivity PSS V = 5% 0.006 0.006 %/% max DD NOTES 1 One LSB = V /4096 V for the 12-bit AD7390. REF 2 The first two codes (000 , 001 ) are excluded from the linearity error measurement. H H 3 These parameters are guaranteed by design and not subject to production testing. 4 Typicals represent average readings measured at 25C. 5 All input control signals are specified with t = t = 2 ns (10% to 90% of 3 V) and timed from a voltage level of 1.6 V. R F 6 The settling time specification does not apply for negative going transitions within the last 3 LSBs of ground. Specifications subject to change without notice. 2 REV. A