3 V, Parallel Input a Dual 12-Bit/10-Bit DACs AD7396/AD7397 FUNCTIONAL BLOCK DIAGRAM FEATURES Micropower: 100 mA/DAC 0.1 mA Typical Power Shutdown V AD7396 DD Single Supply +2.7 V to +5.5 V Operation 12 DACA 12-BIT LDA V OUTA REGISTER DACA Compact 1.1 mm Height TSSOP 24-Lead Package AD7396: 12-Bit Resolution CS INPUTA AD7397: 10-Bit Resolution REGISTER A/B 0.9 LSB Differential Nonlinearity Error 12 1 DATA V REF APPLICATIONS INPUTB Automotive Output Span Voltage REGISTER Portable Communications Digitally Controlled Calibration 12 DACB 12-BIT LDB V OUTB PC Peripherals REGISTER DACB AGND DGND RS SHDN GENERAL DESCRIPTION Both parts are offered in the same pinout, allowing users to The AD7396/AD7397 series of dual, 12-bit and 10-bit voltage- select the amount of resolution appropriate for their applications output digital-to-analog converters are designed to operate from without circuit card changes. a single +3 V supply. Built using a CBCMOS process, these The AD7396/AD7397 are specified for operation over the ex- monolithic DACs offer the user low cost and ease of use in tended industrial (40 C to +85 C) temperature range. The single supply +3 V systems. Operation is guaranteed over the AD7397AR is specified for the 40 C to +125 C automotive supply voltage range of +2.7 V to +5.5 V, making this device temperature range. AD7396/AD7397s are available in plastic ideal for battery operated applications. DIP, and 24-lead SOIC packages. The AD7397ARU is avail- A 12-bit wide data latch loads with a 45 ns write time allowing able for ultracompact applications in a thin 1.1 mm height interface to fast processors without wait states. The double TSSOP 24-lead package. buffered input structure allows the user to load the input registers one at a time, then a single load strobe tied to both 1.0 V = +3V DD LDA+LDB inputs will simultaneously update both DAC out- 0.8 V = +2.5V REF puts. LDA and LDB can also be independently activated to 0.6 immediately update their respective DAC registers. An address input (A/B) decodes DACA or DACB when the chip select CS 0.4 input is strobed. Additionally, an asynchronous RS input sets 0.2 the output to zero-scale at power on or upon user demand. 0.0 Power shutdown to submicroamp levels is directly controlled by 0.2 the active low SHDN pin. While in the power shutdown state register data can still be changed even though the output buffer 0.4 T = +258C, +858C, 558C A is in an open circuit state. Upon return to the normal operating SUPERIMPOSED 0.6 state the latest data loaded in the DAC register will establish the 0.8 output voltage. 1.0 0 512 1024 1536 2048 2560 3072 3584 4096 CODE Decimal Figure 1. DNL vs. Digital Code at Temperature REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or Tel: 781/329-4700 World Wide Web Site: AD7396/AD7397SPECIFICATIONS AD7396 12-BIT ELECTRICAL CHARACTERISTICS ( V = +2.5 V, 408C < T < +858C, unless otherwise noted) REF IN A Parameter Symbol Conditions +3 V 6 10% +5 V 6 10% Units STATIC PERFORMANCE 1 Resolution N 12 12 Bits 2 Relative Accuracy INL T = +25 C 1.75 1.75 LSB max A 2 Relative Accuracy INL T = 40 C, +85 C 2.0 2.0 LSB max A 2 Differential Nonlinearity DNL T = +25 C, Monotonic 0.9 0.9 LSB max A 2 Differential Nonlinearity DNL Monotonic 1 1 LSB max Zero-Scale Error V Data = 000 , T = +25 C, +85 C 4.0 4.0 mV max ZSE H A Zero-Scale Error V Data = 000 , T = 40 C 8.0 8.0 mV max ZSE H A Full-Scale Voltage Error V T = +25 C, +85 C, Data = FFF 8 8mV max FSE A H Full-Scale Voltage Error V T = 40 C, Data = FFF 20 20 mV max FSE A H 3 Full-Scale Tempco TCV 45 45 ppm/ C typ FS REFERENCE INPUT V Range V 0/V 0/V V min/max REF REF DD DD 4 Input Resistance R 2.5 2.5 MW typ REF 3 Input Capacitance C 55pF typ REF ANALOG OUTPUT Output Current (Source) I Data = 800 , D V = 5 LSB 1 1 mA typ OUT H OUT Output Current (Sink) I Data = 800 , D V = 5 LSB 3 3 mA typ OUT H OUT 3 Capacitive Load C No Oscillation 100 100 pF typ L LOGIC INPUTS Logic Input Low Voltage V 0.5 0.8 V max IL Logic Input High Voltage V V 0.6 4.0 V min IH DD Input Leakage Current I 10 10 m A max IL 3 Input Capacitance C 10 10 pF max IL 3, 5 INTERFACE TIMING Chip Select Write Width t 45 35 ns min CS DAC Select Setup t 30 15 ns min AS DAC Select Hold t 0 0 ns min AH Data Setup t 30 15 ns min DS Data Hold t 20 10 ns min DH Load Setup t 20 20 ns min LS Load Hold t 10 10 ns min LH Load Pulsewidth t 30 30 ns min LDW Reset Pulsewidth t 40 30 ns min RSW AC CHARACTERISTICS Output Slew Rate SR Data = 000 to FFF to 000 0.05 0.05 V/m s typ H H H 6 Settling Time t To 0.1% of Full Scale 70 60 m s typ S Shutdown Recovery Time t 90 80 m s typ SDR DAC Glitch Q Code 7FF to 800 to 7FF 65 65 nV/s typ H H H Digital Feedthrough Q 15 15 nV/s typ Feedthrough V /V V = 1.5 V +1 V p-p OUT REF REF DC , Data = 000 , f = 100 kHz 63 63 dB typ H SUPPLY CHARACTERISTICS Power Supply Range V DNL < 1 LSB 2.7/5.5 2.7/5.5 V min/max DD RANGE Positive Supply Current I V = 0 V, No Load 125/200 125/200 m A typ/max DD IL Shutdown Supply Current I SHDN = 0, V = 0 V, No Load 0.1/1.5 0.1/1.5 m A typ/max DD SD IL Power Dissipation P V = 0 V, No Load 600 1000 m W max DISS IL Power Supply Sensitivity PSS D V = 5% 0.006 0.006 %/% max DD NOTES 1 One LSB = V /4096 V for the 12-bit AD7396. REF 2 The first two codes (000 , 001 ) are excluded from the linearity error measurement. H H 3 These parameters are guaranteed by design and not subject to production testing. 4 Typicals represent average readings measured at +25 C. 5 All input control signals are specified with t = t = 2 ns (10% to 90% of +3 V) and timed from a voltage level of +1.6 V. R F 6 The settling time specification does not apply for negative going transitions within the last 3 LSBs of ground. Specifications subject to change without notice. 2 REV. 0