Quad, Serial-Input 12-Bit/10-Bit DACs AD7398/AD7399 FEATURES FUNCTIONAL BLOCK DIAGRAM AD739812-bit resolution V V B V A DD REF REF AD739910-bit resolution AD7398/AD7399 Programmable power shutdown Single (3 V to 5 V) or dual (5 V) supply operation DAC A INPUT DAC A V A REGISTER OUT 3-wire, serial SPI-compatible interface REG A Internal power-on reset SERIAL REGISTER Double buffered registers for simultaneous CS DAC B INPUT DAC B V B multichannel DAC update REGISTER OUT REG B Four separate rail-to-rail reference inputs SDI Thin profile, TSSOP-16 package available DAC C Low tempco: 1.5 ppm/C INPUT V C DAC C REGISTER OUT CLK REG C Qualified for automotive applications 12/10 DAC D APPLICATIONS INPUT DAC D V D REGISTER OUT REG D Automotive output voltage span POWER Portable communications ON RESET Digitally controlled calibration PC peripherals V RS LDAC V C V D GND SS REF REF Figure 1. GENERAL DESCRIPTION The AD7398/AD7399 family of quad, 12-bit/10-bit, voltage Both parts are offered in the same pinout, enabling users to output digital-to-analog converters (DACs) is designed to select the appropriate resolution for their application without operate from a single 3 V to 5 V supply or a dual 5 V supply. redesigning the layout. For 8-bit resolution applications, see the Built with the Analog Devices, Inc. robust CBCMOS process, pin-compatible AD7304 product. these monolithic DACs offer the user low cost with ease-of-use The AD7398/AD7399 are specified over the extended industrial in single or dual-supply systems. (40C to +125C) temperature range. Parts are available in The applied external reference, V , determines the full-scale 16-lead, wide body SOIC and ultracompact, thin, 1.1 mm REF TSSOP packages. output voltage. Valid VREF values include VSS < VREF < VDD that result in a wide selection of full-scale outputs. For multiplying 0.5 V = +5V DD applications, ac inputs can be as large as 5 VP. V = 5V 0.4 SS V = +2.5V REF T = 25C A A doubled-buffered serial-data interface offers high speed, 3-wire, 0.3 SPI- and microcontroller-compatible inputs using serial data-in 0.2 CS (SDI), clock (CLK), and a chip-select ( ). A common level- 0.1 LDAC sensitive, load-DAC strobe ( ) input allows simultaneous 0 update of all DAC outputs from previously loaded input registers. 0.1 Additionally, an internal power-on reset forces the output voltage to 0.2 zero at system turn on. An external asynchronous reset (RS) also 0.3 forces all registers to the zero code state. A programmable power- shutdown feature reduces power dissipation on unused DACs. 0.4 0.5 0 512 1024 1536 2048 2560 3072 3584 4096 CODE (Decimal) Figure 2. AD7398 DNL vs. Code (T = 25C) A Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 20002011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. DNL (LSB) 02179-002 02179-001AD7398/AD7399 TABLE OF CONTENTS Features .............................................................................................. 1 Typical Performance Characteristics ........................................... 10 Applications ....................................................................................... 1 Theory of Operation ...................................................................... 14 Functional Block Diagram .............................................................. 1 DAC Operation .......................................................................... 14 General Description ......................................................................... 1 Operation with VREF Equal to the Supply ................................ 15 Revision History ............................................................................... 2 Power Supply Sequencing ......................................................... 15 Specifications ..................................................................................... 3 Programmable Power Shutdown .............................................. 15 AD7398 12-Bit Voltage Output DAC ........................................ 3 Worst Case Accuracy ................................................................. 15 AD7399 10-Bit Voltage Output DAC ........................................ 4 Serial Data Interface ................................................................... 15 Timing Diagrams .......................................................................... 5 Power-On Reset .......................................................................... 16 Absolute Maximum Ratings ............................................................ 6 Microprocessor Interfacing ....................................................... 16 ESD Caution .................................................................................. 6 Applications Information .............................................................. 18 Pin Configuration And Function Descriptions ............................ 7 Staircase Windows Comparator ............................................... 18 Input Registers .................................................................................. 8 Programmable DAC Reference Voltage .................................. 19 AD7398 Serial Input Register Data Format .............................. 8 Outline Dimensions ....................................................................... 20 AD7399 Serial Input Register Data Format .............................. 8 Ordering Guide .......................................................................... 21 Terminology ...................................................................................... 9 REVISION HISTORY 1/11Rev. B to Rev. C Added Automotive Model and Information .............. Throughout 12/09Rev. A to Rev. B Changes to Ordering Guide .......................................................... 21 6/06Rev. 0 to Rev. A Updated Format .................................................................. Universal Changes to Table 1 ............................................................................ 3 Changes to Table 2 ............................................................................ 4 Changes to Ordering Guide .......................................................... 21 11/00Revision 0: Initial Version Rev. C Page 2 of 24