Quad 12-Bit a D/A Converter AD75004 FUNCTIONAL BLOCK DIAGRAM FEATURES 4 Complete 12-Bit D/A Functions V V REFOUT REFIN Double-Buffered Latches +5V Simultaneous Update of All DACs Possible 2.22k 65 V Output Range VOLTAGE High Stability Bandgap Reference REFERENCE INPUT DAC Monolithic BiMOS Construction LATCHES LATCHES Guaranteed Monotonic over Temperature 12-BIT 10k 8 + 4-BIT 12-BIT DAC LATCHES LATCH V 3/4 LSB Linearity Guaranteed over Temperature OUT3 D7 4 ms max Settling Time to 0.01% D6 12-BIT 10k 8 + 4-BIT 12-BIT Operates with 612 V Supplies D5 TTL DAC LATCHES LATCH V OUT2 D4 INPUTS Low Power: 720 mW max Including Reference D3 8-BIT TTL/5 V CMOS Compatible Logic Inputs D2 BUS 12-BIT 10k 8 + 4-BIT 12-BIT D1 8-Bit Microprocessor Interface DAC LATCHES LATCH V OUT1 D0 24-Pin PDIP or 28-Lead PLCC Package 12-BIT 8 + 4-BIT 12-BIT 10k LATCH LATCHES DAC V OUT0 V PRODUCT DESCRIPTION +12V DD CONTROL LOGIC 12V V SS The AD75004 contains four complete, voltage output, 12-bit AGND digital-to-analog converters, a high stability bandgap reference, AD75004 TTL INPUTS DGND and double-buffered input latches on a single chip. The convert- ers use 12 precision high speed bipolar current steering switches CS WR A3 A2 A1 A0 and laser-trimmed thin-film resistor networks to provide fast settling time and high accuracy. The bandgap reference on the chip has low noise, long term Microprocessor compatibility is achieved by the on-chip stability and temperature drift characteristics comparable to double-buffered latches. The design of the input latches allows discrete reference diodes. The absolute value of the reference is direct interface to 8-bit buses. The 12 bits of data from the first laser trimmed to +5.00 V with 0.6% maximum error. Its tem- rank of latches can then be transferred to the second rank, perature coefficient is also laser trimmed. avoiding generation of spurious analog output values. The latch responds to strobe pulses as short as 50 ns, allowing use with Typical full-scale gain TC is 15 ppm/C. With guaranteed fast microprocessors. monotonicity over the full temperature range, the AD75004 is well suited for wide temperature range performance. The functional completeness and high performance of the AD75004 results from a combination of advanced switch de- sign, the BiMOS II fabrication process, and proven laser trim- ming technology. BiMOS II is an epitaxial BiCMOS process optimized for analog and converter functions. The AD75004 is trimmed at the wafer level and is specified to 1/2 LSB maxi- mum linearity error at 25C and 3/4 LSB over the full operat- ing temperature range. The on-chip output amplifiers provide an output range of 5 V, with 1 LSB equal to 2.44 mV. REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 617/329-4700 Fax: 617/326-8703AD75004SPECIFICATIONS (T = +258C, 612.0 V power supplies unless otherwise noted) A Parameter Symbol Min Typ Max Units DIGITAL INPUTS (D0D7, A0A3, CS, WR) Logic Levels (TTL Compatible) Input Voltage, Logic 1 V 2.0 5.5 V IH Input Voltage, Logic 0 V 0 0.8 V IL Input Current, V = 5.5 V I 10 A IH IH Input Current, V = 0.8 V I 10 A IL IL Input Capacitance C 10 pF IN ACCURACY Resolution 12 Bits Integral Linearity Error 1/4 61/2 LSB Integral Linearity Error, T to T 1/2 3/4 LSB MIN MAX Differential Linearity Error 1/2 63/4 LSB Differential Linearity Error, T to T Guaranteed Monotonic MIN MAX 1 Gain (Full-Scale) Error 2 610 LSB 1 Gain Error Drift, T to T 15 30 ppm/C MIN MAX 1 Bipolar Zero Error 1 62 LSB 1 Bipolar Zero Error Drift, T to T 3 7 ppm/C MIN MAX CHANNEL-TO-CHANNEL MISMATCH Integral Linearity Error 1/2 61 LSB 1 Gain Error 1 64 LSB 1 Bipolar Zero Error 1 62 LSB DYNAMIC PERFORMANCE Settling Time to 0.01% of FSR for FSR Change, 2 k 500 pF Load 2 4 s Slew Rate, 2 k 500 pF Load 5 V/s 2 Digital Input Crosstalk (Static) 50 dB ANALOG OUTPUTS Full-Scale Range (FSR) V 5V OUT Output Current I 5mA OUT Short Circuit Limit Current 640 mA VOLTAGE REFERENCE Reference Output Voltage V 4.97 5.00 5.03 V REFOUT Temperature Coefficient 15 25 ppm/C 3 Reference Output Currents 3.0 5.0 mA Reference Input Voltage V 4.5 5.0 5.5 V REFIN Reference Input Current 5.0 V I 3.0 mA REFIN POWER SUPPLY GAIN SENSITIVITY 1 Gain/V , V = +10.8 to +13.2 V dc 15 625 ppm of FSR/% DD DD 1 Gain/V , V = 10.8 to 13.2 V dc 15 625 ppm of FSR/% SS SS POWER SUPPLY REQUIREMENTS Voltage Range V , V 610.8 12 613.2 V DD SS Supply Currents I , I 25 630 mA DD SS TEMPERATURE RANGE Specification T , T 0 +70 C MIN MAX Storage 65 +150 C NOTES 1 Gain and bipolar zero errors are measured using internal voltage reference and include its errors. 2 Digital crosstalk is defined as the change in any one outputs steady state value as a result of any other output being driven from V to V into a OUTMIN OUTMAX 2 k 500 pF load by means of varying the digital input code. 3 The internal voltage reference is intended to drive on-chip only buffer it if using it externally. 4 All minimum and maximum specifications are guaranteed, and specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. Specifications subject to change without notice. 2 REV. A